{"id":111,"date":"2021-05-19T09:33:09","date_gmt":"2021-05-19T09:33:09","guid":{"rendered":"https:\/\/centres.uohyd.ac.in\/casest\/?page_id=111"},"modified":"2022-10-11T07:26:41","modified_gmt":"2022-10-11T07:26:41","slug":"m-tech-ict","status":"publish","type":"page","link":"https:\/\/centres.uohyd.ac.in\/casest\/m-tech-ict\/","title":{"rendered":"M.tech (ICT)"},"content":{"rendered":"<p>[et_pb_section fb_built=&#8221;1&#8243; fullwidth=&#8221;on&#8221; _builder_version=&#8221;4.16&#8243; global_colors_info=&#8221;{}&#8221;][et_pb_fullwidth_header title=&#8221;M.tech (ICT)&#8221; background_overlay_color=&#8221;rgba(11,188,168,0.76)&#8221; admin_label=&#8221;M.tech (ICT)&#8221; _builder_version=&#8221;4.16&#8243; title_font=&#8221;Trebuchet|700|||||||&#8221; content_font_size=&#8221;16px&#8221; background_image=&#8221;https:\/\/centres.uohyd.ac.in\/casest\/wp-content\/uploads\/sites\/10\/2021\/05\/spring-BW.jpg&#8221; parallax=&#8221;on&#8221; filter_saturate=&#8221;99%&#8221; filter_contrast=&#8221;99%&#8221; child_filter_saturate=&#8221;0%&#8221; child_filter_contrast=&#8221;113%&#8221; z_index_tablet=&#8221;500&#8243; title_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; title_text_shadow_vertical_length_tablet=&#8221;0px&#8221; title_text_shadow_blur_strength_tablet=&#8221;1px&#8221; content_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; content_text_shadow_vertical_length_tablet=&#8221;0px&#8221; content_text_shadow_blur_strength_tablet=&#8221;1px&#8221; subhead_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; subhead_text_shadow_vertical_length_tablet=&#8221;0px&#8221; subhead_text_shadow_blur_strength_tablet=&#8221;1px&#8221; content_link_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; content_link_text_shadow_vertical_length_tablet=&#8221;0px&#8221; content_link_text_shadow_blur_strength_tablet=&#8221;1px&#8221; content_ul_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; content_ul_text_shadow_vertical_length_tablet=&#8221;0px&#8221; content_ul_text_shadow_blur_strength_tablet=&#8221;1px&#8221; content_ol_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; content_ol_text_shadow_vertical_length_tablet=&#8221;0px&#8221; content_ol_text_shadow_blur_strength_tablet=&#8221;1px&#8221; content_quote_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; content_quote_text_shadow_vertical_length_tablet=&#8221;0px&#8221; content_quote_text_shadow_blur_strength_tablet=&#8221;1px&#8221; button_one_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; button_one_text_shadow_vertical_length_tablet=&#8221;0px&#8221; button_one_text_shadow_blur_strength_tablet=&#8221;1px&#8221; button_two_text_shadow_horizontal_length_tablet=&#8221;0px&#8221; button_two_text_shadow_vertical_length_tablet=&#8221;0px&#8221; button_two_text_shadow_blur_strength_tablet=&#8221;1px&#8221; box_shadow_horizontal_tablet=&#8221;0px&#8221; box_shadow_vertical_tablet=&#8221;0px&#8221; box_shadow_blur_tablet=&#8221;40px&#8221; box_shadow_spread_tablet=&#8221;0px&#8221; box_shadow_horizontal_image_tablet=&#8221;0px&#8221; box_shadow_vertical_image_tablet=&#8221;0px&#8221; box_shadow_blur_image_tablet=&#8221;40px&#8221; box_shadow_spread_image_tablet=&#8221;0px&#8221; box_shadow_horizontal_button_one_tablet=&#8221;0px&#8221; box_shadow_vertical_button_one_tablet=&#8221;0px&#8221; box_shadow_blur_button_one_tablet=&#8221;40px&#8221; box_shadow_spread_button_one_tablet=&#8221;0px&#8221; box_shadow_horizontal_button_two_tablet=&#8221;0px&#8221; box_shadow_vertical_button_two_tablet=&#8221;0px&#8221; box_shadow_blur_button_two_tablet=&#8221;40px&#8221; box_shadow_spread_button_two_tablet=&#8221;0px&#8221; text_shadow_horizontal_length_tablet=&#8221;0px&#8221; text_shadow_vertical_length_tablet=&#8221;0px&#8221; text_shadow_blur_strength_tablet=&#8221;1px&#8221; global_colors_info=&#8221;{}&#8221;][\/et_pb_fullwidth_header][\/et_pb_section][et_pb_section fb_built=&#8221;1&#8243; _builder_version=&#8221;4.16&#8243; inner_width_phone=&#8221;50px&#8221; inner_max_width_tablet=&#8221;100px&#8221; inner_max_width_phone=&#8221;50px&#8221; custom_margin=&#8221;-30px|||&#8221; z_index_tablet=&#8221;500&#8243; box_shadow_horizontal_tablet=&#8221;0px&#8221; box_shadow_vertical_tablet=&#8221;0px&#8221; box_shadow_blur_tablet=&#8221;40px&#8221; box_shadow_spread_tablet=&#8221;0px&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_row _builder_version=&#8221;4.16&#8243; _module_preset=&#8221;default&#8221; custom_margin=&#8221;|auto||126px||&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_column type=&#8221;4_4&#8243; _builder_version=&#8221;4.16&#8243; _module_preset=&#8221;default&#8221; global_colors_info=&#8221;{}&#8221;][et_pb_text _builder_version=&#8221;4.17.4&#8243; _module_preset=&#8221;default&#8221; text_text_color=&#8221;#000000&#8243; global_colors_info=&#8221;{}&#8221;]<\/p>\n<p><strong>Name of the Centre: Centre for Advanced Studies in Electronics Science and Technology (CASEST)<\/strong><\/p>\n<p><strong style=\"font-family: 'Rockwell',serif; color: red;\">Vision Statement:<\/strong><\/p>\n<p>To produce skilled human resources for meeting the emerging needs of the country and to execute research in the cutting areas \u00a0in the domain of Electronics Science and Technology.<\/p>\n<p><strong style=\"font-family: 'Rockwell',serif; color: red;\">Mission Statements:<\/strong><\/p>\n<p>MS-1: To emerge as a centre for knowledge generation and skill development in electronics for strategic requirements of the country and sustainable living.<\/p>\n<p>MS2: To train students with critical thinking, problem solving and self learning skills to make them competent for next generation electronics<\/p>\n<p>MS-3: \u00a0To undertake research in emerging technologies involving Integrated Circuits: Design, Tapeout, Test and Measurement, materials to \u00a0devices to circuits: Design, Fabrication and Testing, signal processing and system design<\/p>\n<p>MS-4: \u00a0\u00a0To promote technology transfer and entrepreneurship among the faculty and students.<\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program M.Tech (Integrated Circuits Technology)<\/strong><\/p>\n<p><strong>Program Educational Objectives (PEOs)<\/strong><\/p>\n<p><strong>PEO-1<\/strong>\u00a0To train students in the current technological topics on Integrated Circuits : design, fabrication and testing<\/p>\n<p><strong>PEO-2<\/strong>\u00a0To impart comprehensive knowledge in the emerging technological topics on active and passive devices: materials to devices to circuits: Design, fabrication and testing<\/p>\n<p><strong>PEO-3<\/strong>\u00a0To train students in Device fabrication in class 1000 &amp; class 100 clean room<\/p>\n<p><strong>PEO-4<\/strong>\u00a0To offer training on full cycle development of Integrated circuits, Device design using Electronic Design Automation (EDA) tool.<\/p>\n<p><strong>PEO-4<\/strong>\u00a0To train the students in analytical reasoning, experimental skills and attitude to collaborate between inter-disciplinary research groups<\/p>\n<p style=\"text-align: center;\"><strong>Mapping Program Educational Objectives (PEOs)\u00a0<\/strong><strong>with Mission Statements (MS)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"123\"><strong>\u00a0<\/strong><\/td>\n<td width=\"123\"><strong>MS-1<\/strong><\/td>\n<td width=\"123\"><strong>MS-2<\/strong><\/td>\n<td width=\"123\"><strong>MS-3<\/strong><\/td>\n<td width=\"123\"><strong>MS-4<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"123\"><strong>PEO-1<\/strong><\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"123\"><strong>PEO-2<\/strong><\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"123\"><strong>PEO-3<\/strong><\/td>\n<td width=\"123\">2<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"123\"><strong>PEO-4<\/strong><\/td>\n<td width=\"123\">1<\/td>\n<td width=\"123\">2<\/td>\n<td width=\"123\">2<\/td>\n<td width=\"123\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"123\"><strong>PEO-5<\/strong><\/td>\n<td width=\"123\">2<\/td>\n<td width=\"123\">3<\/td>\n<td width=\"123\">2<\/td>\n<td width=\"123\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Note: \u00a0\u20183\u2019 in the box for \u2018high-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low-level\u2019 mapping.<\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (Integrated Circuits Technology)<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Program Outcomes (POs) <\/strong><\/p>\n<p>After completion of this M.Tech program, the students will be able to<\/p>\n<p>PO-1 Develop scientific and engineering knowledge for design, prototype and testing of devices, Integrated Circuits and systems<\/p>\n<p>PO-2 Collaboration, Teamwork and project management skills<\/p>\n<p>PO-3 Critical thinking for analysis, problem solving and research<\/p>\n<p>PO-4 Promote Entrepreneurship and professional ethics<\/p>\n<p>PO-5 Original thinking, Creativity to solve complex systems and problem formulation<\/p>\n<p>PO-6 Technical presentation and demonstration skills<\/p>\n<p style=\"text-align: center;\"><strong>Program Specific Outcomes (PSOs)<\/strong><\/p>\n<p style=\"text-align: center;\"><strong>(In case of specializations in each academic program, 3 to 4)<\/strong><\/p>\n<p>PSO-1 \u00a0Design and develop efficient VLSI architectures to implement digital systems, digital signal processing \u00a0algorithms and systems on FPGA\/ASIC<\/p>\n<p>PSO-2: \u00a0Design of analog, RF, mixed signal IC and systems for communication, signal processing, and biomedical applications leading to IC tapeout, test and measurement.<\/p>\n<p>PSO-3: Design, simulate, fabricate and test microwave and THz Integrated circuits, MEMS using EDA tool and design concepts.<\/p>\n<p>PSO-4 Design, \u00a0Simulate, fabricate and characterize \u00a0microelectronic devices<\/p>\n<p>PSO-5 Identify the gap and limitations in the current IC technology and propose \u00a0solutions.<\/p>\n<p style=\"text-align: center;\"><strong>Mapping of Program Outcomes (POs) and Program Specific Outcomes (PSOs) with Program Educational Objectives (PEOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"106\"><strong>\u00a0<\/strong><\/td>\n<td width=\"107\"><strong>PEO-1<\/strong><\/td>\n<td width=\"107\"><strong>PEO-2<\/strong><\/td>\n<td width=\"107\"><strong>PEO-3<\/strong><\/td>\n<td width=\"107\"><strong>PEO-4<\/strong><\/td>\n<td width=\"94\"><strong>PEO-5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PO-1<\/strong><\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"94\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PO-2<\/strong><\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"94\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PO-3<\/strong><\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">1<\/td>\n<td width=\"94\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PO-4<\/strong><\/td>\n<td width=\"107\">1<\/td>\n<td width=\"107\">1<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">1<\/td>\n<td width=\"94\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PO-5<\/strong><\/td>\n<td width=\"107\">1<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"94\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PO-6<\/strong><\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"94\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PSO-1<\/strong><\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">1<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"94\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PSO-2<\/strong><\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">1<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"94\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PSO-3<\/strong><\/td>\n<td width=\"107\">1<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"94\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PSO-4<\/strong><\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"94\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"106\"><strong>PSO-5<\/strong><\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">2<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"107\">3<\/td>\n<td width=\"94\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Note: \u20183\u2019 in the box for \u2018high-level\u2019 mapping, 2 for \u2018Medium-level\u2019 mapping, 1 for \u2018Low-level\u2019 mapping.<\/p>\n<p style=\"text-align: center;\"><strong><b>Course Structure \u2013 M. Tech. (ICT)<\/b><\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td colspan=\"4\" width=\"590\"><strong>Semester \u00a0I \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Total No. of Credits : 24<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"91\">Course No.<\/td>\n<td width=\"306\">Title of the course<\/td>\n<td width=\"102\">Contact Hours<\/td>\n<td width=\"91\">Credits<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC401<\/td>\n<td width=\"306\">Semiconductor Device Physics \u00a0and Modeling<\/td>\n<td width=\"102\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC402<\/td>\n<td width=\"306\">Micro \u00a0&amp; Nano Fabrication Technology for ICs<\/td>\n<td width=\"102\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC403<\/td>\n<td width=\"306\">Digital VLSI System Design<\/td>\n<td width=\"102\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC404<\/td>\n<td width=\"306\">RF and Microwave IC&#8217;s<\/td>\n<td width=\"102\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC405<\/td>\n<td width=\"306\">Semiconductor Processing, Characterization and Simulation Laboratory<\/td>\n<td width=\"102\">6<\/td>\n<td width=\"91\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC406<\/td>\n<td width=\"306\">IC \u00a0Design Laboratory<\/td>\n<td width=\"102\">6<\/td>\n<td width=\"91\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC407<\/td>\n<td width=\"306\">RF and Microwave IC Laboratory<\/td>\n<td width=\"102\">4<\/td>\n<td width=\"91\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC 408<\/td>\n<td width=\"306\">Analog and Mixed Signal IC Design<\/td>\n<td width=\"102\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<table>\n<tbody>\n<tr>\n<td colspan=\"4\" width=\"590\"><strong>Semester II \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Total No. of Credits :<\/strong><strong>\u00a0<\/strong><strong>26<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"91\">Course No.<\/td>\n<td width=\"312\">Title of the course<\/td>\n<td width=\"96\">Contact Hours<\/td>\n<td width=\"91\">Credits<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC451<\/td>\n<td width=\"312\">Process, Device and Circuit Modeling and Analysis<\/td>\n<td width=\"96\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC452<\/td>\n<td width=\"312\">MEMS and THz Technology<\/td>\n<td width=\"96\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC453<\/td>\n<td width=\"312\">Digital IC Design<\/td>\n<td width=\"96\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC454<\/td>\n<td width=\"312\">VLSI Signal Processing<\/td>\n<td width=\"96\">4<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC455<\/td>\n<td width=\"312\">\u00a0IC Fabrication Technology Laboratory<\/td>\n<td width=\"96\">8<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC456<\/td>\n<td width=\"312\">MEMS Laboratory<\/td>\n<td width=\"96\">4<\/td>\n<td width=\"91\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC457<\/td>\n<td width=\"312\">IC \u00a0Design Laboratory-II<\/td>\n<td width=\"96\">8<\/td>\n<td width=\"91\">4<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<table>\n<tbody>\n<tr>\n<td colspan=\"4\" width=\"590\"><strong>Semester \u00a0III \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Total No. of Credits : 24<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"91\">Course No.<\/td>\n<td width=\"312\">Title of the course<\/td>\n<td width=\"96\">Contact Hours<\/td>\n<td width=\"91\">Credits<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC458<\/td>\n<td width=\"312\">Project Work + Seminar<\/td>\n<td width=\"96\">\u00a0<\/td>\n<td width=\"91\">24<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<table>\n<tbody>\n<tr>\n<td colspan=\"4\" width=\"590\"><strong>Semester \u00a0IV \u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0Total No. of Credits : 24<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"91\">Course No.<\/td>\n<td width=\"312\">Title of the course<\/td>\n<td width=\"96\">Contact Hours<\/td>\n<td width=\"91\">Credits<\/td>\n<\/tr>\n<tr>\n<td width=\"91\">IC458<\/td>\n<td width=\"312\">Project Work + Dissertation + Viva<\/td>\n<td width=\"96\">Semester<\/td>\n<td width=\"91\">24<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>&nbsp;<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code<strong>: \u00a0IC401<\/strong>\u00a0Title of the course: <strong>Semiconductor Device Physics \u00a0and Modeling<\/strong><\/p>\n<p>L-T-P: \u00a03+1+0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Discuss advanced physical concepts in Semiconductor Electronics such as carrier and impurity statistics, and hot carriers transport effects.<\/p>\n<p>CO-2: Analyze electronic model for the charge distribution at a semiconductor interface as a function of the interface conditions<\/p>\n<p>CO-3: Discuss the operation of several basic semiconductor devices: p-n junctions, metal-semiconductor junctions, Diodes, metal oxide semiconductor field effect transistors (MOSFETs), Complementary MOSFETs (CMOS).<\/p>\n<p>CO-4 : Apply the concepts related to device physics and modelling to solve problems<\/p>\n<p>CO 5: \u00a0Design new problems related to device and modelling<\/p>\n<p style=\"text-align: center;\"><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)\u00a0<\/strong><strong>\u00a0<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td style=\"width: 51px; text-align: center;\"><strong>\u00a0<\/strong><\/td>\n<td style=\"width: 44px;\"><strong>PO1<\/strong><\/td>\n<td style=\"width: 44px;\"><strong>PO2<\/strong><\/td>\n<td style=\"width: 44px;\"><strong>PO3<\/strong><\/td>\n<td style=\"width: 44px;\"><strong>PO4<\/strong><\/td>\n<td style=\"width: 44px;\"><strong>PO5<\/strong><\/td>\n<td style=\"width: 44px;\"><strong>PO6<\/strong><\/td>\n<td style=\"width: 51px;\"><strong>PSO1<\/strong><\/td>\n<td style=\"width: 51px;\"><strong>PSO2<\/strong><\/td>\n<td style=\"width: 51px;\"><strong>PSO3<\/strong><\/td>\n<td style=\"width: 51px;\"><strong>PSO4<\/strong><\/td>\n<td style=\"width: 51px;\"><strong>\u00a0<\/strong><strong>PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td style=\"width: 51px;\"><strong>CO1<\/strong><\/td>\n<td style=\"width: 44px;\">2<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">1<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">2<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">2<\/td>\n<td style=\"width: 51px;\">1<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 51px;\"><strong>CO2<\/strong><\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">1<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">2<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">2<\/td>\n<td style=\"width: 51px;\">1<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 51px;\"><strong>CO3<\/strong><\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">1<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">2<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">2<\/td>\n<td style=\"width: 51px;\">1<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 51px;\"><strong>CO4<\/strong><\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">1<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">2<\/td>\n<td style=\"width: 51px;\">1<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 51px;\"><strong>CO5<\/strong><\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">1<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 44px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">2<\/td>\n<td style=\"width: 51px;\">1<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<td style=\"width: 51px;\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Note: \u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n<p><strong>Detailed syllabus:<\/strong><\/p>\n<p><strong>Unit I<\/strong><\/p>\n<p>Overview of Semiconductor \u00a0Physics- Crystal Structure, Concepts of Band structure, Valence and Conduction bands and Electrons and Holes, Density of States, Carrier statistics, Equilibrium carrier concentrations in intrinsic and doped semi-conductors.<\/p>\n<p>Carrier mobility and scattering mechanisms recombination \/ lifetime due to various mechanisms, determination of carrier mobilities and life times, photoconductivity.<\/p>\n<p><strong>Unit II<\/strong><\/p>\n<p>p-n junctions- Band structures across homogeneous junctions, depletion widths and capacitances of abrupt and linearly graded junctions, current flow through p \u2013n junctions, ideal and practical \u00a0I-V Characteristics, breakdown, heterogeneous junctions<\/p>\n<p><strong>Unit III<\/strong><\/p>\n<p>BJTs: \u00a0current through a BJT, current gain and its dependence on various factors, Ebers-Moll and Gummel-Poon Models<\/p>\n<p><strong>Unit IV<\/strong><\/p>\n<p>Schottky junctions: Metal Semi-conductor junctions, determination of work-functions and barriers heights, Band structures across junctions, Schottky diode and its I-V Characteristics<\/p>\n<p><strong>Unit V<\/strong><\/p>\n<p>Unipolar devices: JFETs, MESFETs, \u00a0MOS structures, Band Structure, CV curves, Strong inversion condition, MOSFET characteristics, depletion and enhancement structures, short-channel and hot-carrier effects, HEMT, HBT<\/p>\n<p>Books:<\/p>\n<p>Physics of Semi-conductor Devices- S.M. Sze<\/p>\n<p>Semi-conductor Devices \u2013 Physics and technology \u00a0&#8211; S. M. Sze<\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC402<\/strong>\u00a0: Title of the course\u00a0:<strong>Micro \u00a0&amp; Nano Fabrication Technology for ICs<\/strong><\/p>\n<p>L-T-P: \u00a03+1+0 \u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Describe the structure and fabrication process steps for the most popular devices.<\/p>\n<p>CO-2: \u00a0Identify the technological problems and their resolution in IC fabrication technology.<\/p>\n<p>CO-3: Distinguish between various processes required for Micro-electronic device fabrication<\/p>\n<p>CO-4: Design and simulate fabrication process steps for specific devices.<\/p>\n<p>CO-5: Evaluate different technologies for selecting a suitable one for a specific device.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs) <\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">0<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong>Note: \u20183\u2019 in the box for \u2018High-level\u2019 mapping, 2 for \u2018Medium-level\u2019 mapping, 1 for \u2018Low\u2019-level\u2019 mapping<\/p>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<p>Unit 1 (10 hours):<\/p>\n<ul>\n<li>Basic Device structures: BJT, MOSFET, MESFET, capacitors, resistors<\/li>\n<li>Design rules, self-alignment, device isolation, oxide breakdown and protection<\/li>\n<li>Process stream\/steps: Bipolar, NMOS, CMOS, GaAsFET, ULSI issues<\/li>\n<\/ul>\n<p>Unit 2 (8 hours):<\/p>\n<ul>\n<li>Wafer fabrication- EGS, Czochralski technique for Si and GaAs, Wafer fab.<\/li>\n<li>Epitaxy: MBE, CVD<\/li>\n<\/ul>\n<p>Unit 3 (6 hours):<\/p>\n<ul>\n<li>Lithography- Photoresists, optical and electron beam lithography<\/li>\n<\/ul>\n<p>Unit 4 (16 hours):<\/p>\n<ul>\n<li>Ion implantation<\/li>\n<li>Oxidation<\/li>\n<li>Thin films deposition- vacuum techniques, sputtering techniques, e-beam and resistive heating evaporation<\/li>\n<li>Etching: wet etching, RIE, RIBE, etchants<\/li>\n<\/ul>\n<p>Unit 5 (4 hours):<\/p>\n<ul>\n<li>Packaging- Die-bonding, wire-bonding, flip-chip technology<\/li>\n<li>Testing and Yield estimation<\/li>\n<li>Clean room methodologies<\/li>\n<\/ul>\n<p>Unit 6:<\/p>\n<ul>\n<li>Self study and seminars (optional as determined by course instructor) : Structure and fabrication technology for memory elements, \u00a0sensors, opto-electronic devices, etc<\/li>\n<\/ul>\n<p>Books:<\/p>\n<ol>\n<li>Science and engineering of microelectronic Fabrication by Stephen Campbell (Oxford University Press; Second edition (2012))<\/li>\n<\/ol>\n<ol start=\"2\">\n<li>VLSI Technology by S.M.Sze (McGraw Hill Education; 2 edition (2017))<\/li>\n<\/ol>\n<ol start=\"3\">\n<li>VLSI Design Techniques for Analog and Digital Circuits by R. L. Geiger, P.E. Allen, and N. R. Strader (McGraw-Hill College (1989))<\/li>\n<\/ol>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC403<\/strong>\u00a0Title of the Course: <strong>Digital VLSI System Design<\/strong><strong>\u00a0<\/strong><\/p>\n<p>L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge : Nil<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Explain \u00a0the principle and steps to implement Digital \u00a0design on FPGA<\/p>\n<p>CO-2: Design, and evaluate combinational and sequential digital sub blocks using different coding styles<\/p>\n<p>CO-3 Analyze the role of different synthesis algorithms and approaches to \u00a0Digital Design.<\/p>\n<p>CO-4 Explain the semicustom and full custom design flow<\/p>\n<p>CO-5 Build a system on chip solution for digital design using FPGA<\/p>\n<p style=\"text-align: center;\"><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs) <\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong>Note: \u00a0\u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<p><strong>Unit -I <\/strong>\u00a0Design styles of IC, VLSI Design flow , Introduction to FPGA, \u00a0The need for a language to design digital circuits, Verilog language elements and data types. Structural style modelling, Data flow modeling, Behavioral modelling.<\/p>\n<p><strong>Unit-II<\/strong>: \u00a0Combinational logic design, Sequential logic design, Arithmetic circuit design, Synthesis of RAM, ROM ,FSM design, FSM Based Modeling of Digital Circuits,<\/p>\n<p><strong>Unit III<\/strong>: \u00a0Logic synthesis: two level, multilevel, high level synthesis algorithms , Technology maping, Timing analysis<\/p>\n<p><strong>Unit IV<\/strong>\u00a0: Physical design: Floor planning, Placement, Cock tree synthesis, detailed routing, packaging, signoff. (Qualitative overview and problem formulation only)<\/p>\n<p><strong>\u00a0<\/strong><strong>Unit V<\/strong>\u00a0: Introduction to embedded system design, system design methodologies, Introduction to System on Chip, \u00a0System on chip design flow, Embedded processor architecture, \u00a0Profiling approach, Hw-SW codesign.<\/p>\n<p><strong>Text books: <\/strong><\/p>\n<ol>\n<li>Verilog Digital System Design <strong><b>RT Level Synthesis, Testbench and Verification<\/b><\/strong>by Navabi, McGraw Hill (2005) ISBN-13:\u00a0978-0071445641<\/li>\n<li>Fundamentals of Digital Logic with Verilog Design, By Stephen Brown, Zvonko Vranesic Tata McGraw-Hill edition.<\/li>\n<li>Computer System Design System-on-Chip Michael J. Flynn Wayne Luk,published by Published by John Wiley &amp; Sons (2011), ISBN 978-0-470-64336-5<\/li>\n<\/ol>\n<p><strong>Reference books: <\/strong><\/p>\n<ol>\n<li>Embedded Core Design with FPGAs, Z. Navabi McGraw Hill (2007), ISBN 978-0-07-147481-8.<\/li>\n<li>Synthesis and optimization of Digital Circuits by G.D.Michelli, Springer.<\/li>\n<\/ol>\n<p>&nbsp;<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC404<\/strong>\u00a0Title of the Course<strong>: RF\/ Microwave ICs<\/strong><\/p>\n<p>L-T-P: 3-1-0 \u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any):<\/p>\n<p>The following courses at the B.Tech or M.Sc level.<\/p>\n<ol>\n<li><strong><b>Electromagnetic Theory<\/b><\/strong><\/li>\n<li><b><\/b><strong><b>Advanced Mathematical Methods<\/b><\/strong><\/li>\n<\/ol>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Analyze\u00a0the difference between high frequency ICs and conventional ICs and apply transmission line and distributed element based approaches to solve problems with high frequency circuits.<\/p>\n<p>CO-2: Apply impedance matching \u00a0techniques for different circuit conditions and frequency ranges. Use of Smith charts.<\/p>\n<p>CO-3 Evaluate\u00a0ways to miniaturize the high frequency passives, interconnects and active devices and also by multilayering.<\/p>\n<p>CO-4 Analyze different types of planar transmission lines and their design considerations.<\/p>\n<p>CO-5 Apply the design approach in planar circuits with filter as an example. (Lumped to distributed conversion).<\/p>\n<p>CO-6 \u00a0Apply softwares to achieve high frequency circuit design goals along with IC 407 course.<\/p>\n<p>CO-7 \u00a0Evaluate emerging high frequency miniaturization techniques through a Term Paper.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO7<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong><strong>Detailed Syllabus:<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong><b>UNIT-1<\/b><\/strong>\u00a0High Frequency Electronics<\/p>\n<p>Why RF communication?, Unique features of RF communication. Lumped vs. Distributed approach. Why RF circuits are to be treated differently in both active and passive devices? How Miniaturization leads to higher frequency operation? Introduction to high frequency ICs. Challenges and ways to miniaturize a high frequency circuit. Hybrid and integrated approach. High frequency ICs with lumped elements. MIC, MMIC and RFICs. Low frequency vs. High frequency models and parameters.<\/p>\n<p><strong><b>UNIT-II<\/b><\/strong>\u00a0Transmission Line Theory, Impedance Transformation and Matching<\/p>\n<p>Review of EM Theory and Transmission lines. Impedance transformation and its effect on microwave circuits. Transmission line sections as circuit elements. Smith chart and admittance chart. Impedance matching techniques for narrow band and broadband operation. Impedance matching using T.line sections, quarter wave lines and lumped elements.<\/p>\n<p><strong>UNIT \u2013III<\/strong>\u00a0Planar Transmission Lines<\/p>\n<p>Planar transmission lines that can be miniaturized: Striplines, Microstriplines, Coplanar waveguides. Design and analysis of microstrip and coplanar waveguide circuits. T.Line discontinuities as circuit elements.<\/p>\n<p><strong>UNIT \u2013IV<\/strong>\u00a0Materials, Fabrication and Miniaturization<\/p>\n<p>Substrates for transmission lines \u2013 dielectrics vs semiconductors. Lumped L,C and R and their models. Parasitics in high frequency circuits and ways to model them.<\/p>\n<p>Materials used for their realization and their properties: Substrates, conductors, semiconductors, dielectrics and magnetic materials. Micromachining for lumped elements and T.Lines, RF MEMS, Integrated inductors and surface integrated waveguides.<\/p>\n<p><strong>UNIT \u2013V<\/strong>\u00a0Microwave Filter Design, Realization and Testing.<\/p>\n<p>Microwave filter design. Filters using transmission line sections. Kuroda\u2019s Identities. Richard\u2019s transformation. Microwave Resonators, Filters using resonators, Varactors and tuning techniques, On wafer probing and on wafer calibration techniques.<\/p>\n<p><strong><em><b>Text Books:<\/b><\/em><\/strong><\/p>\n<p>David M. Pozar, \u201cMicrowave Engineering,\u201d 2nd Edition, John Wiley 1998, ISBN 0-471-17096-8.<\/p>\n<p>Peter A. Rizzi, \u201cMicrowave Engineering \u2013 Passive Circuits\u201d, PHI, ISBN \u00a081-203-1461-1<\/p>\n<p>I.D. Robertson and S.Lucyszyn, \u00a0RFIC and MMIC design and technology, , IEE Circuits, Devices and Systems Series 13. ISBN-10 : 0852967861<\/p>\n<p><strong>Related IEEE Journal Papers<\/strong><\/p>\n<p><strong><em><i>Reference Books: <\/i><\/em><\/strong><\/p>\n<p>K.C. Gupta, Ramesh Garg, Inder Bahl, and Prakash Bhartia, \u201cMicrostrip Lines and Slotlines,\u201d Artech House, 2nd edition, 1996, ISBN: 089006766X.<\/p>\n<p>T.C. Edwards and M. B. Steer, \u201cFoundations of Interconnect and Microstrip Design,\u201d John Wiley &amp; Sons, 3rd edition, 2001, ISBN: 0471607010.<\/p>\n<p>Mike Golio (Ed.), The RF and Microwave Handbook, CRC Press. ISBN: 9780849385926.<\/p>\n<p>Novel technologies for microwave and millimeter-wave applications, Jean-Fu Kiang, Kluwer Academic Publishers. ISBN -10: 1441954015.<\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC405<\/strong><\/p>\n<p>Title of the course: <strong>Semiconductor Processing, Characterization and Simulation Laboratory<\/strong><\/p>\n<p>L-T-P: \u00a01-0-5 \u00a0 Credits: 3<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Basics of semiconductor devices and methods of fabrication, at BTech level.<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Process various materials\/layers of a modern semiconductor device, analyze physical behavior and correlate with performance.<\/p>\n<p>CO-2: Test discrete semiconductor devices using an industry standard method,\u00a0analyse and interpret results.<\/p>\n<p>CO-3: Characterize semiconductors for their applications in device fabrication.<\/p>\n<p>CO-4: Explain the concepts of various device simulation program.<\/p>\n<p>CO-5: Simulate device and circuit performance: Application, validation and\u00a0interpretation of results.<\/p>\n<p>CO-5: Evaluate the performance of various semiconductor devices and\u00a0Circuits.<\/p>\n<p>CO-6: Communicate the results of all experiments in the form of a written\u00a0technical report.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<ol>\n<li>Thin film deposition by physical vapour deposition and characterization<\/li>\n<li>Synthesis of novel 2D materials such as graphene<\/li>\n<li>Thermal oxidation of Si<\/li>\n<li>Device characterization using Device Analyser<\/li>\n<li>Estimation of Optical Band gap of a semiconductor<\/li>\n<li>Process Simulation-(ion implantation, diffusion, oxidation)<\/li>\n<li>Device Simulation- (p-n Diode, Schottky diode, MOSFET)<\/li>\n<li>Circuit Simulation- \u00a0(MOSFET based circuits)<\/li>\n<\/ol>\n<p><strong>Text books: <\/strong><\/p>\n<ol>\n<li>&#8220;Semiconductor Material and Device Characterization&#8221; by Dieter K. Schroder (Wiley-IEEE Press; 3 edition (2015))<\/li>\n<li>Science and engineering of microelectronic Fabrication by Stephen Campbell Oxford (University Press; Second edition (2012))<\/li>\n<li>VLSI Technology M.Sze (McGraw Hill Education; 2 edition (2017))<\/li>\n<\/ol>\n<p><strong><b>\u00a0<\/b><\/strong><\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC406<\/strong>\u00a0Title of the Course:\u00a0\u00a0<strong>IC Design Laboratory-1<\/strong><\/p>\n<p>L-T-P: \u00a00-0-6 \u00a0\u00a0 Credits: 3<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): IC402 and IC403 courses<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Design and verify the functionality of \u00a0\u00a0combinational and sequential circuits using Verilog HDL.<\/p>\n<p>CO2: Implement and carry-out on chip debugging of the digital design on FPGA.<\/p>\n<p>CO3: Design and simulate the basic analog integrated circuits like CMOS amplifiers and biasing circuits.<\/p>\n<p>CO4: Design of integrated circuits for target specifications and checking the robustness of the design at different process corners<\/p>\n<p>CO5: Implement physical design of integrated circuits, DRC and LVS check, post-layout extracted simulation.<\/p>\n<p>CO6: Communicate the results of the experiment in the form of written technical report.<\/p>\n<p><strong>Mapping of Course Outcomes (Cos) with Program Outcomes (Pos) <\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><strong>\u00a0<\/strong><strong>\u00a0<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">&#8211;<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">&#8211;<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong><strong>Detailed syllabus: <\/strong><\/p>\n<p>List of experiments and mini-projects<\/p>\n<p>1: Vivado Design Flow<\/p>\n<p>2: Synthesizing a RTL Design<\/p>\n<p>3: Implementing the Design<\/p>\n<p>4: Using the IP Catalog and IP Integrator<\/p>\n<p>5: Hardware Debugging<\/p>\n<p>6: Analog and Mixed Signal IC Design Lab Projects<\/p>\n<ol>\n<li>CS and CG amplifiers with different loads, e.g., resistive, diode connected, current source<\/li>\n<li>Current mirrors, e.g., basic current mirror, cascode current mirror<\/li>\n<li>Differential amplifier<\/li>\n<li>Operational Transconductance amplifiers<\/li>\n<\/ol>\n<p><strong>Name of the \u00a0Centre : CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC407<\/strong>\u00a0\u00a0Title of the Course:\u00a0<strong>RF\/ Microwave IC Laboratory<\/strong><\/p>\n<p>L-T-P: \u00a00-0-4 \u00a0\u00a0 Credits: 2<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): It is the Lab component of the IC403 RF\/Microwave ICs Course.<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Apply microwave measurement techniques using advanced measurement facilities like VNA.<\/p>\n<p>CO-2: Apply the usage of EDA tools in doing high frequency circuit Design and Simulation.<\/p>\n<p>CO-3 Apply EDA tools to Design and Simulate passive MIC circuits and active microwave circuits.<\/p>\n<p>CO-4 Apply EDA tools for doing Full wave simulations by Method of Moments, FEM and FDTD.<\/p>\n<p>CO-5 Analyze EDA tools to do Fullwave simulation and analysis of layout of high frequency circuits.<\/p>\n<p>CO-6 Create high frequency circuits using EDA tools and simulate them.<\/p>\n<p>CO-7 Fabricate the high frequency circuits.<\/p>\n<p>CO-8 Communicate the results of these experiments in the form of a written technical report.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs) <\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"45\"><strong>PO1<\/strong><\/td>\n<td width=\"45\"><strong>PO2<\/strong><\/td>\n<td width=\"45\"><strong>PO3<\/strong><\/td>\n<td width=\"45\"><strong>PO4<\/strong><\/td>\n<td width=\"45\"><strong>PO5<\/strong><\/td>\n<td width=\"45\"><strong>PO6<\/strong><\/td>\n<td width=\"54\"><strong>PSO1<\/strong><\/td>\n<td width=\"54\"><strong>PSO2<\/strong><\/td>\n<td width=\"54\"><strong>PSO3<\/strong><\/td>\n<td width=\"54\"><strong>PSO4<\/strong><\/td>\n<td width=\"54\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">2<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">2<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO7<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO8<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">1<\/td>\n<td width=\"45\">1<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">1<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>List of experiments<\/strong><strong>\/ Mini -projects<\/strong><\/p>\n<ol>\n<li>Microwave measurement techniques for devices and circuits with Vector Network Analyzer, Power Meter and On Wafer Probing System.<\/li>\n<li>Tools for high frequency design, Familiarization of EDA tools for RF\/ Microwave IC design and simulation, Usage of Models and Libraries for EDA tools, Design Examples (using both active and passive devices).<\/li>\n<li>Fullwave analysis in simulation and analysis of circuit layouts and housings using Method of Moments, FEM and FDTD.<\/li>\n<li>Design and simulation of active and passive microwave integrated circuits using EDA tools.\n<ul>\n<li>The list of passive circuits includes: Dividers, Filters, Couplers, Tees, Circulators etc<\/li>\n<li>The list of active circuits includes : Amplifiers, oscillators, switches, phase shifters, mixers etc<\/li>\n<li><em>Design and Simulation of some of the above circuits\/ devices will be done in the classes and remaining to be done as assignments.<\/em><\/li>\n<\/ul>\n<\/li>\n<\/ol>\n<ol start=\"5\">\n<li>Fabrication and characterization of at least one of the above devices (<em>in project mode. Extending to Semester break<\/em>).<\/li>\n<\/ol>\n<p>References:<\/p>\n<ol>\n<li><a href=\"https:\/\/www.amazon.in\/Practical-Circuit-Design-Wireless-Systems\/dp\/1580535224\/ref=sr_1_1?keywords=les+besser+microwave&amp;qid=1579246871&amp;s=books&amp;sr=1-1\"><u>Practical RF Circuit Design for Modern Wireless Systems: Active Circuits and Systems Vol I and II<\/u><\/a>, Les Besser and Rowan Gilmore. Artech House, ISBN-10:1580535224<\/li>\n<li>RF circuit design, by Christopher Bowick, Elsevier. <strong><b>ISBN-10:<\/b><\/strong>0750685182<\/li>\n<li>Reading Material provided by the EDA tool used.<\/li>\n<li>\u00a0100 ADS Design Examples: Based on the Textbook: RF and Microwave Circuit Design, Ali A. Behagi,ISBN-10:0996446621, Techno Search.<\/li>\n<li>Related IEEE Papers.<\/li>\n<\/ol>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p><strong><b>Course Code: \u00a0IC408 Title of the Course: <\/b><\/strong><strong><b>Analog and Mixed Signal IC Design<\/b><\/strong><strong><b>\u00a0<\/b><\/strong><\/p>\n<p>L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course, the students will be able to<\/p>\n<p>CO 1: Apply the knowledge of different biasing styles for different electronic circuits (Apply level)<\/p>\n<p>CO 2: Design basic building blocks of analog ICs up to layout level.(Apply)<\/p>\n<p>CO 3: Develop a procedure for optimal compensation of op-amp against\u00a0process, supply and temperature variations (Apply)<\/p>\n<p>CO 4: Identify suitable topologies of the constituent sub-systems and\u00a0corresponding circuits as per the specifications of the system (Analyze)<\/p>\n<p>CO 5: Design an optimally compensated Op-amp including parasitic effects up\u00a0to the \u00a0tape-out (create level)<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"44\"><strong>\u00a0<\/strong><\/td>\n<td width=\"43\"><strong>PO1<\/strong><\/td>\n<td width=\"43\"><strong>PO2<\/strong><\/td>\n<td width=\"43\"><strong>PO3<\/strong><\/td>\n<td width=\"43\"><strong>PO4<\/strong><\/td>\n<td width=\"43\"><strong>PO5<\/strong><\/td>\n<td width=\"43\"><strong>PO6<\/strong><\/td>\n<td width=\"53\"><strong>PSO1<\/strong><\/td>\n<td width=\"53\"><strong>PSO2<\/strong><\/td>\n<td width=\"53\"><strong>PSO3<\/strong><\/td>\n<td width=\"53\"><strong>PSO4<\/strong><\/td>\n<td width=\"53\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO1<\/strong><\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO2<\/strong><\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO3<\/strong><\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO4<\/strong><\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO5<\/strong><\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong>Note: \u00a0\u20183\u2019 in the box for \u2018High-level\u2019 mapping, 2 for \u2018Medium-level\u2019 mapping, 1 for \u2018Low\u2019-level\u2019 mapping<\/p>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong><u>Course Contents:<\/u><\/strong><\/p>\n<p><strong><u>Unit-1: <\/u><\/strong>MOS Device Structure and Circuit Models, Single-Stage and Differential Amplifiers, Passive and Active Current Mirrors, single- &amp; multi-stage amplifier design<\/p>\n<p><strong><u>Unit-2: <\/u><\/strong>Frequency Response of Amplifiers, Noise, Feedback, Op Amp Design, Stability and Frequency Compensation<\/p>\n<p><strong><b>Unit-3:<\/b><\/strong>\u00a0Bandgap References, Introduction to Switched-Capacitor Circuits, Analog and Mixed Signal Layout Design Flow<\/p>\n<p><strong><b>Unit-4:<\/b><\/strong>\u00a0Introduction to Switched Capacitor Circuits, Sampling circuits and architecture Introduction to Data convertors, digital to analog conversion, analog to digital conversion and oversampled converters<\/p>\n<p>================================================================<\/p>\n<p><strong>Text books: <\/strong><\/p>\n<ol start=\"4\">\n<li>Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.<\/li>\n<\/ol>\n<p><strong>Reference books: <\/strong><\/p>\n<ol>\n<li>R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, 2001, Wiley.<\/li>\n<li>A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.<\/li>\n<li>Synthesis and optimization of Digital Circuits by G. D. Michelli, Springer.<\/li>\n<\/ol>\n<p>&nbsp;<\/p>\n<p><strong>Name of the Centre : CASEST<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Name of the Academic Program M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0IC451: Process , Device and Circuit Modeling and Analysis<\/p>\n<p>L-T-P: \u00a03+1+0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Nill<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Define \u00a0physics involved in modelling of semiconductor device<\/p>\n<p>CO-2: Apply knowledge of mathematics, science, and engineering to design and analysis of modern analog integrated circuits.<\/p>\n<p>CO-3: Compose research\/investigation, design and development work to solve problems faced by the industry<\/p>\n<p>CO-4 : Evaluate the True roots using Open method: Newton\u2019s Rapson method, secant method and multiple Newton Rapson method and understand the pitfalls of Gauss Elimination Method<\/p>\n<p>CO-5: Explain the CMOS fabrication, device and process integration using technology computer-aided designed (TCAD) simulation tools.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><strong>\u00a0<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Unit I<\/strong><\/p>\n<p>Process Simulation \u2013 Overview of basic FET ad BJT process flows, physical models and simulation techniques for unit process such as etching, thermal oxidation, diffusion, ion implantation and process integration.<\/p>\n<p><strong>Unit II<\/strong><\/p>\n<p><strong>\u00a0<\/strong>Device Modeling &#8211; Overview of basic device structures (BJT, FET and MOSFETs), basic concepts of Carrier transport; drift-diffusion, hydrodynamic, energy balance. \u00a0Numerical methods, meshing (fixed &amp; adaptive), numerical solutions, common methods (Newton, Gummel etc.), DC &amp; AC simulation, transient simulation, Monte Carlo,<\/p>\n<p><strong>Unit III<\/strong><\/p>\n<p>DC electrical simulation; thermionic current, Fowler Nordheim tunneling, direct tunnel current, damage, interface states, trap assisted tunneling, lattice heating, thermal properties of device, thermal boundaries, Metal &amp; dielectic modeling, RC delays. Future trends in TCAD, 3-D modeling,<\/p>\n<p><strong>Unit IV<\/strong><\/p>\n<p>Circuit Simulation \u2013Nodal equations, Linear Equation Solution, Gaussian elimination and LU factorization, Linear dc and transient analysis, Sparse matrix behavior, Nonlinear Equation Solution, Transient Simulation, Convergence<\/p>\n<p><strong>Text &amp; Reference Books:<\/strong><\/p>\n<ol>\n<li>S. Yuan, J.J. Liou, Semiconductor Device Physics and Simulation<\/li>\n<li>S Selberherr, Analysis and Simulation of Semiconductor Devices<\/li>\n<li>L. Pillage, R. A. Rohrer, and C. Visweswariah, Electronic Circuit &amp; System Simulation Methods<\/li>\n<li>Silicon VLSI Technology: Fundamentals, Practice, and Modeling, Jim Plummer, Michael D. Deal, and Peter B. Griffin<\/li>\n<\/ol>\n<p>&nbsp;<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC452<\/strong>\u00a0\u00a0Title of the Course:\u00a0<strong>MEMS and THz Technology<\/strong><\/p>\n<p>L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): B.Tech or M.Sc in an area related to Electronics or Physics.<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Analyze the emergent technologies for MEMS as well as THz technology \u00a0and evaluate the need and relevance of these technologies in emerging Communication technologies.<\/p>\n<p>CO-2: Analyze why micromachining is important for sensors and the issues involved in their design, fabrication and signal transduction.<\/p>\n<p>CO-3 Evaluate the Bulk and Surface micromachining technologies and applicability of \u00a0Micromachining in the high frequency Electronics.<\/p>\n<p>CO-4 Explain the THz frequency range, \u00a0the difficulties in using this part of the spectrum \u00a0and the solutions available as well as emerging, \u00a0to overcome these difficulties.<\/p>\n<p>CO-5 Apply the technologies, devices and circuits using semiconductors that are available or emerging \u00a0to realize communication in THz range of frequencies.<\/p>\n<p>CO-6 Evaluate the importance of \u00a0MEMS and THz technologies in emerging security and communication technologies.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>Detailed Syllabus<\/strong><\/p>\n<p><strong>Unit -1<\/strong><\/p>\n<p>Micromachining vs. Microelectronics, Micromachining and Electronics. Microsystems, Scaling laws<\/p>\n<p><strong><b>Unit -II<\/b><\/strong><\/p>\n<p>MEMS and Sensors, Silicon and other substrates for MEMS. Micromachining processes.<\/p>\n<p>Signal transduction methods, MEMS IN RF Electronics. MEMS Design and packaging.<\/p>\n<p><strong><b>Unit- III<\/b><\/strong><\/p>\n<p>THz range of em spectrum. Atmospheric propagation characteristics of THz radiation.<\/p>\n<p>Why THz in Electronics? Active devices for THz operation. Passive devices for THz operation.<\/p>\n<p>Materials for THz technology.<\/p>\n<p><strong><b>Unit- IV<\/b><\/strong><\/p>\n<p>Surface Integrated Waveguides and micromachined components for THz operation. \u00a0THz circuits for communication. THz for security applications. Design and simulation of THz circuits.<\/p>\n<p><strong>Unit \u2013V \u00a0Assignment:<\/strong>\u00a0What is the circuitry required to use a particular commercial MEMS device in an application?<\/p>\n<p><strong><b>References:<\/b><\/strong><\/p>\n<ol>\n<li><b><\/b> Microsystem Design by Stephen D Seturia, Springer, ISBN-10 : 9788181285461<\/li>\n<li>MEMS &amp; Microsystems design and Manufacture, Tai-Ran Hsu, McGraw Hill Education, ISBN 10- 007048709X<\/li>\n<li>Semiconductor Terahertz technology: Devices and Systems at Room Temperature Operation. By Guillermo Carpintero et.al, IEEE Press., ISBN -13: 978-1118920428<\/li>\n<\/ol>\n<p><strong>Related IEEE Journal Papers<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code:<strong><b>\u00a0\u00a0IC453 <\/b><\/strong>Title of the Course<strong><b>: <\/b><\/strong><strong><b>Digital IC Design<\/b><\/strong><strong><b>\u00a0<\/b><\/strong><\/p>\n<p>L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course, the students will be able to<\/p>\n<p>CO1 Design CMOS inverters with specified noise margin and propagation delay.<\/p>\n<p>CO2 Implement efficient techniques at circuit level for improving power and speed of digital circuits<\/p>\n<p>CO3 Identify sources of power consumption in a given VLSI Circuit<\/p>\n<p>CO4 Estimate dynamic and leakage power components in a DSM\u00a0VLSI circuit<\/p>\n<p>CO5 Analyze the dynamic and leakage power components in a DSM\u00a0VLSI circuit<\/p>\n<p>CO6 Estimate power consumption at different levels of abstraction in a VLSI\u00a0system.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"44\"><strong>\u00a0<\/strong><\/td>\n<td width=\"43\"><strong>PO1<\/strong><\/td>\n<td width=\"43\"><strong>PO2<\/strong><\/td>\n<td width=\"43\"><strong>PO3<\/strong><\/td>\n<td width=\"43\"><strong>PO4<\/strong><\/td>\n<td width=\"43\"><strong>PO5<\/strong><\/td>\n<td width=\"43\"><strong>PO6<\/strong><\/td>\n<td width=\"53\"><strong>PSO1<\/strong><\/td>\n<td width=\"53\"><strong>PSO2<\/strong><\/td>\n<td width=\"53\"><strong>PSO3<\/strong><\/td>\n<td width=\"53\"><strong>PSO4<\/strong><\/td>\n<td width=\"53\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO1<\/strong><\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO2<\/strong><\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO3<\/strong><\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO4<\/strong><\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>CO5<\/strong><\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">1<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"44\"><strong>C06<\/strong><\/td>\n<td width=\"43\">1<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"43\">3<\/td>\n<td width=\"43\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">2<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">3<\/td>\n<td width=\"53\">1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Note: \u00a0\u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<p><strong>Unit-1<\/strong>: INTRODUCTION: A Historical Perspective; Issues in Digital Integrated Circuit Design; Quality Metrics of a Digital Design; Cost of an Integrated Circuit; Functionality and Robustness; Performance; Power and Energy Consumption; A Word on Process Variations; Perspective: Technology Scaling, More than Moore, New Technologies like: FDSOI, FINFET, 3D IC\u2019s. etc., Interconnect Parameters \u2014 Capacitance, Resistance, and Inductance; Electrical Wire Models; The Ideal Wire; The Lumped Model; The Lumped RC model; The Distributed rc Line; The Transmission Line; SPICE Wire Models; Distributed rc Lines in SPICE; Transmission Line Models in SPICE.<\/p>\n<p><strong>Unit-2<\/strong>: THE CMOS INVERTER: The Static CMOS Inverter \u2014 An Intuitive Perspective; Evaluating the Robustness of the CMOS Inverter: The Static Behaviour; \u00a0Switching Threshold; Noise Margins; Robustness Revisited; Performance of CMOS Inverter: The Dynamic Behaviour; Computing the Capacitances; Propagation Delay: First-Order Analysis; Propagation Delay from a Design Perspective; Power, Energy, and Energy-Delay; Dynamic Power Consumption; Static Consumption; Putting It All Together; Analysing Power Consumption; Technology Scaling and its Impact on the Inverter Metrics.<\/p>\n<p><strong>Unit-3<\/strong>: DESIGNING COMBINATIONAL AND SEQUENTIAL CIRCUITS: Static CMOS Design; Complementary CMOS; Ratioed Logic; \u00a0Pass-Transistor Logic; Dynamic CMOS Design; How to Choose a Logic Style; Designing Logic for Reduced Supply Voltages. \u00a0Timing Metrics for Sequential Circuits; Classification of Memory Elements; Static Latches and Registers; The Bistability Principle; Multiplexer-Based Latches; Master-Slave Edge-Triggered Register; Low-Voltage Static Latches; Static SR Flip-Flops\u2014Writing Data by Pure Force; \u00a0Dynamic Latches and Registers; Dynamic Transmission-Gate Edge-triggered Registers; C2MOS\u2014A Clock-Skew Insensitive Approach ; True Single-Phase Clocked Register (TSPCR).<\/p>\n<p><strong>Unit-4:<\/strong> TIMING ISSUES IN DIGITAL CIRCUITS: Timing Classification of Digital Systems; Synchronous Interconnect; Mesochronous interconnect; Plesiochronous Interconnect; Asynchronous Interconnect; Synchronous Design \u2014 An In-depth Perspective; Synchronous Timing Basics; Sources of Skew and Jitter; Clock-Distribution Techniques. Latch-Based Clocking, Clocking in IC\u2019s: Basic Concepts PLL and DLL; Building Blocks of a PLL; Future Directions and Perspectives; Distributed Clocking Using DLLs; Synchronous versus Asynchronous Design.<\/p>\n<p><strong><b>Text Books:<\/b><\/strong><\/p>\n<p>Jan Rabaey, AnanthaChandrakasan, and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edition, Prentice Hall, 2003.<\/p>\n<p><strong><b>Reference Books:<\/b><\/strong><\/p>\n<p>N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition, Addison-Wesley, 2005.<\/p>\n<p>D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd edition, McGraw Hill, 2004.<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC454<\/strong>\u00a0Title of the Course:\u00a0<strong>VLSI Signal processing<\/strong><\/p>\n<p>L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge : IC403 course<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Explain \u00a0the methodologies to design custom or semicustom VLSI circuits of \u00a0DSP algorithms.<\/p>\n<p>CO-2: Apply \u00a0\u00a0speed\/area\/power optimized architectural techniques to DSP algorithms.<\/p>\n<p>CO-3 Analyze the role of different architectural techniques on target performance indicators<\/p>\n<p>CO-4 Design a DSP system using FPGA<\/p>\n<p>CO-5 Create new architecture for different DSP units\/subunits<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><strong>\u00a0<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p>Note: \u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n<p><strong>Detailed syllabus<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Unit-1<\/strong><\/p>\n<p>DSP Algorithm Design \u2013 DSP Representation (Data-flow, Control-flow, Signal-flow graphs and block diagrams), filter structures, Iteration bound, Longest Path Matrix algorithm,<\/p>\n<p><strong>Unit-II<\/strong><\/p>\n<p>Circuit and Architecture Design \u2013 Hardware design of real and complex multiplication and addition. \u00a0Pipelining, parallel processing, Retiming<\/p>\n<p><strong>Unit III:<\/strong>\u00a0Unfolding, Folding, Systolic architecture design, Fast Convolution algorithms<\/p>\n<p><strong>Unit- IV<\/strong><\/p>\n<p>Algorithm strength reduction in Filters, Bit level arithmetic architectures: bit-parallel, bit-serial Multiplier, Distributed arithmetic architecture,<\/p>\n<p><strong>Unit-V <\/strong><\/p>\n<p>Speed\/area optimized architecture for matrix multiplication, matrix inversion, CORDIC architecture, Speed\/area optimized architecture of \u00a0FFT, redundant number systems, scaling and round off noise, \u00a0Case study- 1: \u00a0FPGA of implementation of artificial neural network, case study -2: FPGA implementation of Orthogonal matching Pursuit algorithm,<\/p>\n<p>Books recommended:<\/p>\n<ol>\n<li>K. Parhi \u2013 VLSI Digital Signal Processing Systems \u2013 Design and Implementation, Wiley publication (2015 reprint)<\/li>\n<li>Roger Woods, John McAllister, Gaye Lightbody, Ying Yi, FPGA-based implementation of Signal Processing systems, Wiley publication (2008)<\/li>\n<\/ol>\n<p>References:<\/p>\n<ul>\n<li>Pramod Kumar Meher, On Efficient Retiming Of Fixed-Point Circuits, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016<\/li>\n<li>Supriya Aggarwal, Pramod K. Meher, And Kavita Khare Concept, Design, And Implementation Of Reconfigurable CORDIC , IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 24, NO. 4, APRIL 2016<\/li>\n<li>Lakshmi, B. And Dhar, A. S.CORDIC Architectures: A Survey, VLSI Design, Hindwai, \u00a0Volume\u00a02010\u00a0, Article ID\u00a0794891<\/li>\n<li>IEEE papers related to VLSI signal processing<\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0IC455 : Title of the course<strong>: \u00a0IC Fabrication Technology Laboratory<\/strong><\/p>\n<p>L-T-P: \u00a01-0-7 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Gain hands on experience and skills in Micro-electronic device processing and clean-room practices involved in Integrated Circuit fabrication industry.<\/p>\n<p>CO-2: Analyze the process protocols\/steps followed in IC fabrication technology.<\/p>\n<p>CO-3: Analyze the physical reasons that are limiting the current fabrication technology and Propose new procedures to overcome these limits.<\/p>\n<p>CO-4: Fabricate and test GaAs based Schottky Diode and MESFET structures.<\/p>\n<p>CO-5: Fabricate and test Si based Schottky Diode and MOS Capacitor.<\/p>\n<p>CO-6: Discuss the role of processing in device functionalities and propose new \/ alternate device structures \/ parameters \/ processes.<\/p>\n<p>CO-7: Communicate the results of all experiments in the form of a written\u00a0technical report.<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">0<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">1<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">1<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">3<\/td>\n<td width=\"47\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO7<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">0<\/td>\n<td width=\"47\">2<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>Detailed Syllabus:<\/strong><\/p>\n<ol>\n<li>Layout Design, Use of design rules, layout design of 1 CMOS circuit<\/li>\n<li>Processing introduction: Substrate\/waferscribing\/cleaving, Substrate\/wafer wafer cleaning, spin-coating, lithography, etch and lift-offprocess for obtaining patterned deposited layers<\/li>\n<li>GaAs processing and lithography: Process steps for GaAs (implanted\/multilayer wafer) to pattern for carrier concentration, mobility measurements and optionally FET.<\/li>\n<li>Thin film deposition by sputtering, evaporation and spin coating<\/li>\n<li>Fabrication of Ohmic contacts, Schottky Diode and MOS Capacitor.<\/li>\n<li>Testing.<\/li>\n<\/ol>\n<p><strong>Text books: <\/strong><\/p>\n<ol>\n<li>&#8220;Semiconductor Material and Device Characterization&#8221; by Dieter K. Schroder (Wiley-IEEE Press; 3 edition (2015))<\/li>\n<li>\u201cThe Science and Engineering of Microelectronic Fabrication\u201d by Stephen A Campbell (Oxford University Press; Second edition (2012))<\/li>\n<li>\u201cVLSI Technology\u201d by S.M. Sze (McGraw Hill Education; 2 edition (2017))<\/li>\n<\/ol>\n<p>&nbsp;<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code<strong>: \u00a0<\/strong><strong>IC456<\/strong>\u00a0\u00a0Title of the Course<strong>:<\/strong><strong>\u00a0MEMS Technology<\/strong><strong>\u00a0Laboratory<\/strong><\/p>\n<p>L-T-P: \u00a00-0-4 \u00a0\u00a0 Credits: 2<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): IC 452 MEMS and THz course (Theory).<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: \u00a0Apply EDA tools working with Finite Element Method and the concept of Multiphysics and the conditions and constraints under which these techniques work.<\/p>\n<p>CO-2 : Apply EDA tools to create \u00a03D structures that function as MEMS or Surface Integrated Waveguide devices.<\/p>\n<p>CO-3 : Create MEMS devices using EDA tools suitable for sensing and communication applications and simulate them under the influence of different stimuli using Multiphysics techniques.<\/p>\n<p>CO-4 : \u00a0Create MEMS structures suitable for RF and THz range applications.<\/p>\n<p>CO-5 : Create RF or Sensor device by SIW technology (Fabricate it after simulation and test them experimentally with connectorization).<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"45\"><strong>PO1<\/strong><\/td>\n<td width=\"45\"><strong>PO2<\/strong><\/td>\n<td width=\"45\"><strong>PO3<\/strong><\/td>\n<td width=\"45\"><strong>PO4<\/strong><\/td>\n<td width=\"45\"><strong>PO5<\/strong><\/td>\n<td width=\"45\"><strong>PO6<\/strong><\/td>\n<td width=\"54\"><strong>PSO1<\/strong><\/td>\n<td width=\"54\"><strong>PSO2<\/strong><\/td>\n<td width=\"54\"><strong>PSO3<\/strong><\/td>\n<td width=\"54\"><strong>PSO4<\/strong><\/td>\n<td width=\"54\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">2<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">2<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">2<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"45\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">2<\/td>\n<td width=\"54\">3<\/td>\n<td width=\"54\">1<\/td>\n<td width=\"54\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><b> <\/b><strong><b>Detailed syllabus:<\/b><\/strong><\/p>\n<p>Lab Experiments<\/p>\n<ol>\n<li>EDA tools for MEMS design and simulation, Familiarization of EDA tools. Modeling, material attributes, meshing and elements, choice of solvers, loads and load steps, post processing.<\/li>\n<\/ol>\n<ol start=\"2\">\n<li>Coupled field simulation using Multiphysics, 3D structure drawing in EDA tools, Design Examples.<\/li>\n<\/ol>\n<ol start=\"3\">\n<li>Simulation of a cantilever structure \u2013 Model, Harmonic and Transient analysis, Cantilever based chemical sensor design \u2013 by mass sensing route, Cantilever based RF switch, Membrane based RF switch, Membrane based piezoresistive \u00a0pressure sensor, Interdigitated \u00a0structure based MEMS devices and Otical micromirror. Any other examples suggested by the instructer.<\/li>\n<\/ol>\n<ol start=\"4\">\n<li>Design and simulate SIW based structures suitable for RF or sensing applications. It\u2019s fabrication using composite polymer substrates and testing after connectorization.<\/li>\n<li>Design and simulation of MEMS based sensors or RF \/ THz devices and presentation of the results as a project report.<\/li>\n<\/ol>\n<p><strong><b>References:<\/b><\/strong><\/p>\n<ol>\n<li>Materials provided by the EDA tool: Offline and online.<\/li>\n<li>MEMS: A Practical Guide of Design, Analysis, and Applications:<b><\/b>by <a href=\"https:\/\/www.amazon.in\/s\/ref=dp_byline_sr_book_1?ie=UTF8&amp;field-author=Jan+Korvink&amp;search-alias=stripbooks\"><u>Jan Korvink<\/u><\/a>, <a href=\"https:\/\/www.amazon.in\/s\/ref=dp_byline_sr_book_2?ie=UTF8&amp;field-author=Oliver+Paul&amp;search-alias=stripbooks\"><u>Oliver Paul<\/u><\/a>, Springer, ISBN-13: 978-3662568354<\/li>\n<\/ol>\n<p>&nbsp;<\/p>\n<p><strong>Name of the \u00a0Centre :CASEST<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC457<\/strong>\u00a0Title of the Course:\u00a0\u00a0<strong>IC Design Laboratory-1I<\/strong><\/p>\n<p>L-T-P: \u00a00-0-8 \u00a0\u00a0 Credits: 4<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): IC402 and IC403<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n<p>CO-1: Understand the fixed point accuracy vs bitlength, Understand pipelining in detail.<\/p>\n<p>CO2: Design and implement DSP on \u00a0FPGA<\/p>\n<p>CO3: Design and a System on Chip using FPGA<\/p>\n<p>CO4: \u00a0Implement CMOS Inverters, logic gates in full-custom IC design flow.<\/p>\n<p>CO5: Estimate power consumption and propagation delay by pre-layout and post-layout simulations<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><strong>\u00a0<\/strong><\/p>\n<table style=\"height: 140px;\">\n<tbody>\n<tr style=\"height: 25px;\">\n<td style=\"height: 25px; width: 47px;\"><strong>\u00a0<\/strong><\/td>\n<td style=\"height: 25px; width: 40px;\"><strong>PO1<\/strong><\/td>\n<td style=\"height: 25px; width: 40px;\"><strong>PO2<\/strong><\/td>\n<td style=\"height: 25px; width: 40px;\"><strong>PO3<\/strong><\/td>\n<td style=\"height: 25px; width: 40px;\"><strong>PO4<\/strong><\/td>\n<td style=\"height: 25px; width: 40px;\"><strong>PO5<\/strong><\/td>\n<td style=\"height: 25px; width: 40px;\"><strong>PO6<\/strong><\/td>\n<td style=\"height: 25px; width: 47px;\"><strong>PSO1<\/strong><\/td>\n<td style=\"height: 25px; width: 47px;\"><strong>PSO2<\/strong><\/td>\n<td style=\"height: 25px; width: 47px;\"><strong>PSO3<\/strong><\/td>\n<td style=\"height: 25px; width: 47px;\"><strong>PSO4<\/strong><\/td>\n<td style=\"height: 25px; width: 47px;\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr style=\"height: 23px;\">\n<td style=\"height: 23px; width: 47px;\"><strong>CO1<\/strong><\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">&#8211;<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<\/tr>\n<tr style=\"height: 23px;\">\n<td style=\"height: 23px; width: 47px;\"><strong>CO2<\/strong><\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">&#8211;<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<\/tr>\n<tr style=\"height: 23px;\">\n<td style=\"height: 23px; width: 47px;\"><strong>CO3<\/strong><\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<\/tr>\n<tr style=\"height: 23px;\">\n<td style=\"height: 23px; width: 47px;\"><strong>CO4<\/strong><\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<\/tr>\n<tr style=\"height: 23px;\">\n<td style=\"height: 23px; width: 47px;\"><strong>CO5<\/strong><\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">3<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 40px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">2<\/td>\n<td style=\"height: 23px; width: 47px;\">3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>Detailed syllabus: <\/strong><\/p>\n<p>List of Experiments and Mini-projects:<\/p>\n<p>1: FIR filter design using MATLAB<\/p>\n<p>2: \u00a0Fixed point simulation in MATLAB<\/p>\n<p>3: Design and synthesis of FIR filter<\/p>\n<p>4: CIC filter and pipelining Design and synthesis of FIR filter<\/p>\n<p>5: Adding Peripherals in Programmable Logic<\/p>\n<p>6: Creating and Adding Custom IP<\/p>\n<p>7: Debugging using Vivado Logic Analyzer cores<\/p>\n<p>8: CMOS Logic gates design<\/p>\n<p>9: Estimation of power consumption and propagation delay of CMOS circuits.<\/p>\n<p><strong>Name of the Centre: CASEST<\/strong><\/p>\n<p><strong>\u00a0<\/strong><strong>Name of the Academic Program M.Tech (IC Technology)<\/strong><\/p>\n<p>Course Code: \u00a0<strong>IC458<\/strong>\u00a0Title of the Course<strong>:<\/strong><strong>\u00a0\u00a0Project work+seminar+Dissertation+viva<\/strong><\/p>\n<p>L-T-P: Credits: 48<\/p>\n<p>Prerequisite Course \/ Knowledge (If any): First two semester course works<\/p>\n<p><strong>Course Outcomes (COs) <\/strong><\/p>\n<p><strong>\u00a0<\/strong>After completion of the first two semester course work each student will do a two semester project in any area related to their study. After the completion of the one semester of the project work, the students will be able to<\/p>\n<p>CO-1: \u00a0Carryout literature survey in the field of study<\/p>\n<p>CO2: \u00a0Define the problem.<\/p>\n<p>CO3: Formulate the objectives and hypothesis.<\/p>\n<p>CO4: \u00a0Communicate in the form of technical seminar<\/p>\n<p>After the completion of the second semester of the project work, the students will be able to<\/p>\n<p>CO5: Execute the experimental study in order to achieve the defined objectives<\/p>\n<p>CO6: Implement the objective<\/p>\n<p>CO7: Analyse and interpret the results<\/p>\n<p>CO8: Communicate the results of the entire study in the form of technical<\/p>\n<p><strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong><strong>and Program Specific Outcomes (PSOs)<\/strong><\/p>\n<table>\n<tbody>\n<tr>\n<td width=\"47\"><strong>\u00a0<\/strong><\/td>\n<td width=\"40\"><strong>PO1<\/strong><\/td>\n<td width=\"40\"><strong>PO2<\/strong><\/td>\n<td width=\"40\"><strong>PO3<\/strong><\/td>\n<td width=\"40\"><strong>PO4<\/strong><\/td>\n<td width=\"40\"><strong>PO5<\/strong><\/td>\n<td width=\"40\"><strong>PO6<\/strong><\/td>\n<td width=\"47\"><strong>PSO1<\/strong><\/td>\n<td width=\"47\"><strong>PSO2<\/strong><\/td>\n<td width=\"47\"><strong>PSO3<\/strong><\/td>\n<td width=\"47\"><strong>PSO4<\/strong><\/td>\n<td width=\"47\"><strong>\u00a0<\/strong><strong style=\"font-family: inherit; font-size: inherit;\">PSO5<\/strong><\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO1<\/strong><\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO2<\/strong><\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO3<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO4<\/strong><\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2`<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO5<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO6<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO7<\/strong><\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<tr>\n<td width=\"47\"><strong>CO8<\/strong><\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">1<\/td>\n<td width=\"40\">2<\/td>\n<td width=\"40\">3<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">\u00a0<\/td>\n<td width=\"47\">2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<p><strong>\u00a0<\/strong><\/p>\n<p>[\/et_pb_text][\/et_pb_column][\/et_pb_row][\/et_pb_section]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Name of the Centre: Centre for Advanced Studies in Electronics Science and Technology (CASEST) Vision Statement: To produce skilled human resources for meeting the emerging needs of the country and to execute research in the cutting areas \u00a0in the domain of Electronics Science and Technology. Mission Statements: MS-1: To emerge as a centre for knowledge [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_et_pb_use_builder":"on","_et_pb_old_content":"","_et_gb_content_width":"","footnotes":""},"_links":{"self":[{"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/pages\/111"}],"collection":[{"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/comments?post=111"}],"version-history":[{"count":20,"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/pages\/111\/revisions"}],"predecessor-version":[{"id":451,"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/pages\/111\/revisions\/451"}],"wp:attachment":[{"href":"https:\/\/centres.uohyd.ac.in\/casest\/wp-json\/wp\/v2\/media?parent=111"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}