{"id":117,"date":"2021-05-19T09:34:41","date_gmt":"2021-05-19T09:34:41","guid":{"rendered":"https:\/\/centres.uohyd.ac.in\/casest\/?page_id=117"},"modified":"2022-10-11T09:44:20","modified_gmt":"2022-10-11T09:44:20","slug":"m-tech-mvlsi","status":"publish","type":"page","link":"https:\/\/centres.uohyd.ac.in\/casest\/m-tech-mvlsi\/","title":{"rendered":"M.tech (MVLSI)"},"content":{"rendered":"

[et_pb_section fb_built=”1″ fullwidth=”on” _builder_version=”4.16″ global_colors_info=”{}”][et_pb_fullwidth_header title=” M.tech (MVLSI)” background_overlay_color=”rgba(11,188,168,0.76)” admin_label=” M.tech (MVLSI)” _builder_version=”4.16″ title_font=”Trebuchet|700|||||||” content_font_size=”16px” background_image=”https:\/\/centres.uohyd.ac.in\/casest\/wp-content\/uploads\/sites\/10\/2021\/05\/spring-BW.jpg” parallax=”on” filter_saturate=”99%” filter_contrast=”99%” child_filter_saturate=”0%” child_filter_contrast=”113%” z_index_tablet=”500″ title_text_shadow_horizontal_length_tablet=”0px” title_text_shadow_vertical_length_tablet=”0px” title_text_shadow_blur_strength_tablet=”1px” content_text_shadow_horizontal_length_tablet=”0px” content_text_shadow_vertical_length_tablet=”0px” content_text_shadow_blur_strength_tablet=”1px” subhead_text_shadow_horizontal_length_tablet=”0px” subhead_text_shadow_vertical_length_tablet=”0px” subhead_text_shadow_blur_strength_tablet=”1px” content_link_text_shadow_horizontal_length_tablet=”0px” content_link_text_shadow_vertical_length_tablet=”0px” content_link_text_shadow_blur_strength_tablet=”1px” content_ul_text_shadow_horizontal_length_tablet=”0px” content_ul_text_shadow_vertical_length_tablet=”0px” content_ul_text_shadow_blur_strength_tablet=”1px” content_ol_text_shadow_horizontal_length_tablet=”0px” content_ol_text_shadow_vertical_length_tablet=”0px” content_ol_text_shadow_blur_strength_tablet=”1px” content_quote_text_shadow_horizontal_length_tablet=”0px” content_quote_text_shadow_vertical_length_tablet=”0px” content_quote_text_shadow_blur_strength_tablet=”1px” button_one_text_shadow_horizontal_length_tablet=”0px” button_one_text_shadow_vertical_length_tablet=”0px” button_one_text_shadow_blur_strength_tablet=”1px” button_two_text_shadow_horizontal_length_tablet=”0px” button_two_text_shadow_vertical_length_tablet=”0px” button_two_text_shadow_blur_strength_tablet=”1px” box_shadow_horizontal_tablet=”0px” box_shadow_vertical_tablet=”0px” box_shadow_blur_tablet=”40px” box_shadow_spread_tablet=”0px” box_shadow_horizontal_image_tablet=”0px” box_shadow_vertical_image_tablet=”0px” box_shadow_blur_image_tablet=”40px” box_shadow_spread_image_tablet=”0px” box_shadow_horizontal_button_one_tablet=”0px” box_shadow_vertical_button_one_tablet=”0px” box_shadow_blur_button_one_tablet=”40px” box_shadow_spread_button_one_tablet=”0px” box_shadow_horizontal_button_two_tablet=”0px” box_shadow_vertical_button_two_tablet=”0px” box_shadow_blur_button_two_tablet=”40px” box_shadow_spread_button_two_tablet=”0px” text_shadow_horizontal_length_tablet=”0px” text_shadow_vertical_length_tablet=”0px” text_shadow_blur_strength_tablet=”1px” global_colors_info=”{}”][\/et_pb_fullwidth_header][\/et_pb_section][et_pb_section fb_built=”1″ _builder_version=”4.16″ inner_width_phone=”50px” inner_max_width_tablet=”100px” inner_max_width_phone=”50px” custom_margin=”-30px|||” z_index_tablet=”500″ box_shadow_horizontal_tablet=”0px” box_shadow_vertical_tablet=”0px” box_shadow_blur_tablet=”40px” box_shadow_spread_tablet=”0px” global_colors_info=”{}”][et_pb_row _builder_version=”4.16″ _module_preset=”default” global_colors_info=”{}”][et_pb_column type=”4_4″ _builder_version=”4.16″ _module_preset=”default” global_colors_info=”{}”][et_pb_text _builder_version=”4.17.4″ _module_preset=”default” global_colors_info=”{}”]<\/p>\n

Name of the Centre: Centre for Advanced Studies in Electronics Science and Technology (CASEST)<\/strong><\/p>\n

Name of the Academic Program M.Tech (<\/strong>Microelectronics & VLSI Design<\/strong>)<\/strong><\/p>\n

Program Educational Objectives (PEOs)<\/strong><\/p>\n

PEO-1<\/strong>\u00a0To train students in the current technological topics on Integrated Circuits : design, fabrication and testing<\/p>\n

PEO-2<\/strong>\u00a0To impart comprehensive knowledge in the emerging technological topics on active and passive devices: materials to devices to circuits: Design, fabrication and testing<\/p>\n

PEO-3<\/strong>\u00a0To train students in Device fabrication in class 1000 & class 100 clean room<\/p>\n

PEO-4<\/strong>\u00a0To offer training on full cycle development of Integrated circuits, Device design using Electronic Design Automation (EDA) tool.<\/p>\n

PEO-4<\/strong>\u00a0To train the students in analytical reasoning, experimental skills and attitude to collaborate between inter-disciplinary research groups<\/p>\n

Mapping Program Educational Objectives (PEOs)<\/strong><\/p>\n

with Mission Statements (MS)<\/strong><\/p>\n\n\n\n\n\n\n\n\n
\u00a0<\/strong><\/td>\nMS-1<\/strong><\/td>\nMS-2<\/strong><\/td>\nMS-3<\/strong><\/td>\nMS-4<\/strong><\/td>\n<\/tr>\n
PEO-1<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PEO-2<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PEO-3<\/strong><\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PEO-4<\/strong><\/td>\n1<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
PEO-5<\/strong><\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Note: \u00a0\u20183\u2019 in the box for \u2018high-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low-level\u2019 mapping.<\/p>\n

Name of the Centre: CASEST<\/strong><\/p>\n

\u00a0<\/strong>Name of the Academic Program \u00a0M.Tech (<\/strong>Microelectronics & VLSI Design<\/strong>)<\/strong><\/p>\n

\u00a0<\/strong>Program Outcomes (POs) <\/strong><\/p>\n

After completion of this M.Tech program, the students will be able to<\/p>\n

PO-1 Develop scientific and engineering knowledge for design, prototype and testing of devices, Integrated Circuits and systems<\/p>\n

PO-2 Collaboration, Teamwork and project management skills<\/p>\n

PO-3 Critical thinking for analysis, problem solving and research<\/p>\n

PO-4 Promote Entrepreneurship and professional ethics<\/p>\n

PO-5 Original thinking, Creativity to solve complex systems and problem formulation<\/p>\n

PO-6 Technical presentation and demonstration skills<\/p>\n

Program Specific Outcomes (PSOs)<\/strong><\/p>\n

PSO-1 \u00a0Design and develop efficient VLSI architectures to implement digital systems, signal processing \u00a0algorithms and systems .<\/p>\n

PSO-2: \u00a0Design of analog, RF, mixed signal ASIC and systems leading to IC tape-out, test and measurement.<\/p>\n

PSO-3: Design, simulate, fabricate and test microwave Integrated circuits, MEMS using EDA tool and design concepts.<\/p>\n

PSO-4 Exposure to design, simulate and fabricate microelectronic devices<\/p>\n

PSO-5 Identify techniques to improve the EDA tool to minimize design productivity gap.
<\/strong><\/p>\n

Mapping of Program Outcomes (POs) and Program Specific Outcomes (PSOs) with Program Educational Objectives (PEOs)<\/strong>\u00a0<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\u00a0<\/strong><\/td>\nPEO-1<\/strong><\/td>\nPEO-2<\/strong><\/td>\nPEO-3<\/strong><\/td>\nPEO-4<\/strong><\/td>\nPEO-5<\/strong><\/td>\n<\/tr>\n
PO-1<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
PO-2<\/strong><\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PO-3<\/strong><\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
PO-4<\/strong><\/td>\n1<\/td>\n1<\/td>\n2<\/td>\n1<\/td>\n2<\/td>\n<\/tr>\n
PO-5<\/strong><\/td>\n1<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
PO-6<\/strong><\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
PSO-1<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PSO-2<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PSO-3<\/strong><\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
PSO-4<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n<\/tr>\n
PSO-5<\/strong><\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Note: \u20183\u2019 in the box for \u2018high-level\u2019 mapping, 2 for \u2018Medium-level\u2019 mapping, 1 for \u2018Low-level\u2019 mapping.<\/p>\n

Syllabus Structure of M.Tech (Microelectronics & VLSI Design)<\/u><\/strong><\/p>\n

Semester \u2013I<\/strong>\u00a0 No. of credits – 27<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n
Course No<\/td>\nTitle of the course<\/td>\nNo. of Contact Hours<\/td>\nNo. of Credits<\/td>\n<\/tr>\n
MV401<\/td>\nSemiconductor Device Physics and Modelling<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
MV402<\/td>\nAnalog and Mixed Signal IC Design<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
MV403<\/td>\nDigital VLSI System Design<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
MV404<\/td>\nRF Devices and Circuits<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
MV405<\/td>\nNumerical techniques for Microelectronics Simulation<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
MV406<\/td>\nMicroelectronics Simulation Lab<\/td>\n4<\/td>\n2<\/td>\n<\/tr>\n
MV407<\/td>\nIC Design Lab<\/td>\n6<\/td>\n3<\/td>\n<\/tr>\n
MV408<\/td>\nRF IC Lab<\/td>\n4<\/td>\n2<\/td>\n<\/tr>\n
MV409<\/td>\nSemester Project -I<\/td>\n4<\/td>\n2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Semester \u2013II<\/strong>\u00a0 No. of credits \u2013 25<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n
Course No.<\/td>\nTitle of the course<\/td>\nNo. of Contact Hours<\/td>\nNo.of Credits<\/td>\n<\/tr>\n
MV451<\/td>\nDigital IC Design<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
MV452<\/td>\nNano Fabrication Lab<\/td>\n8<\/td>\n4<\/td>\n<\/tr>\n
\u00a0<\/td>\nElective \u00a0I<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
\u00a0<\/td>\nElective II<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
\u00a0<\/td>\nElective III<\/td>\n4<\/td>\n4<\/td>\n<\/tr>\n
MV453<\/td>\nSemester Project -II<\/td>\n6<\/td>\n3<\/td>\n<\/tr>\n
MV454<\/td>\nSeminar + Comprehensive Viva<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Semester \u2013III<\/strong>\u00a0 \u00a0No. of credits \u2013 24<\/strong><\/p>\n\n\n\n\n
Course No<\/td>\nTitle of the course<\/td>\nNo of Credits<\/td>\n<\/tr>\n
MV501<\/td>\nProject work + seminar<\/td>\n24<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Semester \u2013IV<\/strong>\u00a0 \u00a0No. of credits \u2013 24<\/strong><\/p>\n\n\n\n\n\n
Course No<\/td>\nTitle of the course<\/td>\nNo of Credits<\/td>\n<\/tr>\n
MV 501<\/td>\nProject work + Dissertation +Viva<\/td>\n24<\/td>\n<\/tr>\n
\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/strong>List of Electives:<\/strong>\u00a0A student can choose three electives combining from Stream A and stream B, However, he\/she need to choose minimum one from each stream. A particular elective will be offered depending on the available expertise and \u00a0student group size (minimum number of 6 students are required to offer an elective)<\/p>\n

\u00a0<\/strong>Stream A:<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n
MV461: VLSI Test and Verification<\/td>\n<\/tr>\n
MV462:VLSI CAD algorithms<\/td>\n<\/tr>\n
MV463:Special Topics in Analog and Mixed Signal IC Design<\/td>\n<\/tr>\n
MV464:Wireless Communication IC Design<\/td>\n<\/tr>\n
MV465:VLSI Signal Processing<\/td>\n<\/tr>\n
MV466:Microsystems Modeling and Design<\/td>\n<\/tr>\n
MV474: High speed VLSI and system on chip: Design and implementation<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Stream B:<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n
MV467:Sensors, Science and Technology<\/td>\n<\/tr>\n
MV468:Thin Film Technology<\/td>\n<\/tr>\n
MV469:Advanced RF Devices and Circuits<\/td>\n<\/tr>\n
MV470:III-V Compound Semiconductors<\/td>\n<\/tr>\n
MV471:Nano Technology<\/td>\n<\/tr>\n
MV472:MEMS and THz Technology<\/td>\n<\/tr>\n
MV473:Optoelectronics<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

 <\/p>\n

Name of the \u00a0Centre :CASEST<\/strong><\/p>\n

\u00a0<\/strong>Name of the Academic Program \u00a0: M.Tech (Microelectronics & VLSI Design)<\/strong><\/p>\n

Course Code: \u00a0MV401<\/strong><\/p>\n

Title of the course: Semiconductor Device Physics and Modeling<\/strong><\/p>\n

L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n

Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n

\u00a0<\/strong>Course Outcomes (COs) <\/strong><\/p>\n

\u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n

CO-1: Discuss advanced physical concepts in Semiconductor Electronics such as carrier and impurity statistics, and hot carriers transport effects.<\/p>\n

CO-2: Analyze electronic model for the charge distribution at a semiconductor interface as a function of the interface conditions<\/p>\n

CO-3: Discuss the operation of several basic semiconductor devices: p-n junctions, metal-semiconductor junctions, Diodes, metal oxide semiconductor field effect transistors (MOSFETs), Complementary MOSFETs (CMOS).<\/p>\n

CO-4 : Apply the concepts related to device physics and modelling to solve problems<\/p>\n

CO 5: \u00a0Design new problems related to device and modelling<\/p>\n

Mapping of Course Outcomes (COs) with Program Outcomes (POs)\u00a0<\/strong>and Program Specific Outcomes (PSOs)<\/strong>\u00a0<\/strong><\/p>\n\n\n\n\n\n\n\n\n
\u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\u00a0<\/strong>PSO5<\/strong><\/td>\n<\/tr>\n
CO1<\/strong><\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
CO2<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
CO3<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
CO4<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
CO5<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Note: \u00a0\u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n

Detailed Syllabus:<\/strong><\/p>\n

\u00a0<\/strong>Unit I<\/strong><\/p>\n

Overview of Semiconductor \u00a0Physics- Crystal Structure, Concepts of Band structure, Valence and Conduction bands and Electrons and Holes, Density of States, Carrier statistics, Equilibrium carrier concentrations in intrinsic and doped semi-conductors.<\/p>\n

Carrier mobility and scattering mechanisms recombination \/ lifetime due to various mechanisms, determination of carrier mobilities and life times, photoconductivity.<\/p>\n

Unit II<\/strong><\/p>\n

p-n junctions- Band structures across homogeneous junctions, depletion widths and capacitances of abrupt and linearly graded junctions, current flow through p \u2013n junctions, ideal and practical \u00a0I-V Characteristics, breakdown, heterogeneous junctions<\/p>\n

Unit III<\/strong><\/p>\n

BJTs: \u00a0current through a BJT, current gain and its dependence on various factors, Ebers-Moll and Gummel-Poon Models<\/p>\n

Unit IV<\/strong><\/p>\n

Schottky junctions: Metal Semi-conductor junctions, determination of work-functions and barriers heights, Band structures across junctions, Schottky diode and its I-V Characteristics<\/p>\n

Unit V<\/strong><\/p>\n

Unipolar devices: JFETs, MESFETs, \u00a0MOS structures, Band Structure, CV curves, Strong inversion condition, MOSFET characteristics, depletion and enhancement structures, short-channel and hot-carrier effects, HEMT, HBT<\/p>\n

Books:<\/p>\n

Physics of Semi-conductor Devices- S.M. Sze<\/p>\n

Semi-conductor Devices \u2013 Physics and technology \u00a0– S. M. Sze<\/p>\n

Name of the \u00a0Centre :CASEST<\/strong><\/p>\n

\u00a0<\/strong>Name of the Academic Program \u00a0: M.Tech (Microelectronics & VLSI Design)<\/strong><\/p>\n

Course Code:\u00a0\u00a0MV402 <\/b><\/strong>Title of the Course:\u00a0<\/b><\/strong>Analog and Mixed Signal IC Design<\/b><\/strong>\u00a0<\/b><\/strong><\/p>\n

L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n

Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n

Course Outcomes (COs) <\/strong><\/p>\n

\u00a0<\/strong>After completion of this course, the students will be able to<\/p>\n

CO 1: Apply the knowledge of different biasing styles for different electronic circuits (Apply level)<\/p>\n

CO 2: Design basic building blocks of analog ICs up to layout level.(Apply)<\/p>\n

CO 3: Develop a procedure for optimal compensation of op-amp against process, supply and temperature variations (Apply)<\/p>\n

CO 4: Identify suitable topologies of the constituent sub-systems and corresponding circuits as per the specifications of the system (Analyze)<\/p>\n

CO 5: Design an optimally compensated Op-amp including parasitic effects up to the \u00a0tape-out (create level)<\/p>\n

Mapping of Course Outcomes (COs) with Program Outcomes (POs)<\/strong><\/p>\n

and Program Specific Outcomes (PSOs)<\/strong><\/p>\n\n\n\n\n\n\n\n\n
\u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\u00a0<\/strong>PSO5<\/strong><\/td>\n<\/tr>\n
CO1<\/strong><\/td>\n2<\/td>\n2<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n2<\/td>\n<\/tr>\n
CO2<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n<\/tr>\n
CO3<\/strong><\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n<\/tr>\n
CO4<\/strong><\/td>\n1<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n<\/tr>\n
CO5<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\u00a0<\/strong>Note: \u00a0\u20183\u2019 in the box for \u2018High-level\u2019 mapping, 2 for \u2018Medium-level\u2019 mapping, 1 for \u2018Low\u2019-level\u2019 mapping<\/p>\n

Detailed Syllabus:<\/strong><\/p>\n

Course Contents:<\/u><\/strong><\/p>\n

Unit-1: <\/u><\/strong>MOS Device Structure and Circuit Models, Single-Stage and Differential Amplifiers, Passive and Active Current Mirrors, single- & multi-stage amplifier design<\/p>\n

Unit-2: <\/u><\/strong>Frequency Response of Amplifiers, Noise, Feedback, Op Amp Design, Stability and Frequency Compensation<\/p>\n

Unit-3:<\/b><\/strong>\u00a0Bandgap References, Introduction to Switched-Capacitor Circuits, Analog and Mixed Signal Layout Design Flow<\/p>\n

Unit-4:<\/b><\/strong>\u00a0Introduction to Switched Capacitor Circuits, Sampling circuits and architecture Introduction to Data convertors, digital to analog conversion, analog to digital conversion and oversampled converters<\/p>\n

=============================================================<\/p>\n

Text books: <\/strong><\/p>\n

    \n
  1. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.<\/li>\n<\/ol>\n

    Reference books: <\/strong><\/p>\n

      \n
    1. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th Edition, 2001, Wiley.<\/li>\n
    2. A. Johns and K. Martin, Analog Integrated Circuit Design, Wiley, 1997.<\/li>\n
    3. Synthesis and optimization of Digital Circuits by G. D. Michelli, Springer.<\/li>\n<\/ol>\n

       <\/p>\n

      Name of the \u00a0Centre :CASEST<\/strong><\/p>\n

      Name of the Academic Program \u00a0M.Tech (Microelectronics & VLSI Design)<\/strong><\/p>\n

      Course Code: \u00a0MV403<\/strong>\u00a0Title of the Course: Digital VLSI System Design<\/strong>\u00a0<\/strong><\/p>\n

      L-T-P: \u00a03-1-0 \u00a0\u00a0 Credits: 4<\/p>\n

      Prerequisite Course \/ Knowledge : Nil<\/p>\n

      Course Outcomes (COs) <\/strong><\/p>\n

      \u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n

      CO-1: Explain \u00a0the principle and steps to implement Digital \u00a0design on FPGA<\/p>\n

      CO-2: Design, and evaluate combinational and sequential digital sub blocks using different coding styles<\/p>\n

      CO-3 Analyze the role of different synthesis algorithms and approaches to \u00a0Digital Design.<\/p>\n

      CO-4 Explain the semicustom and full custom design flow<\/p>\n

      CO-5 Build a system on chip solution for digital design using FPGA<\/p>\n

      Mapping of Course Outcomes (COs) with Program Outcomes (POs)<\/strong><\/p>\n

      and Program Specific Outcomes (PSOs)<\/strong><\/p>\n\n\n\n\n\n\n\n\n
      \u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\u00a0<\/strong>PSO5<\/strong><\/td>\n<\/tr>\n
      CO1<\/strong><\/td>\n2<\/td>\n2<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n2<\/td>\n<\/tr>\n
      CO2<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n\u00a0<\/td>\n2<\/td>\n<\/tr>\n
      CO3<\/strong><\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n\u00a0<\/td>\n1<\/td>\n\u00a0<\/td>\n1<\/td>\n<\/tr>\n
      CO4<\/strong><\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
      CO5<\/strong><\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n\u00a0<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

      \u00a0<\/strong>Note: \u00a0\u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n

      Detailed Syllabus:<\/strong><\/p>\n

      \u00a0<\/strong>Unit -I <\/strong>\u00a0Design styles of IC, VLSI Design flow , Introduction to FPGA, \u00a0The need for a language to design digital circuits, Verilog language elements and data types. Structural style modelling, Data flow modeling, Behavioral modelling.<\/p>\n

      Unit-II<\/strong>: \u00a0Combinational logic design, Sequential logic design, Arithmetic circuit design, Synthesis of RAM, ROM ,FSM design, FSM Based Modeling of Digital Circuits,<\/p>\n

      Unit III<\/strong>: \u00a0Logic synthesis: two level, multilevel, high level synthesis algorithms , Technology maping, Timing analysis<\/p>\n

      Unit IV<\/strong>\u00a0: Physical design: Floor planning, Placement, Cock tree synthesis, detailed routing, packaging, signoff. (Qualitative overview and problem formulation only)<\/p>\n

      Unit V<\/strong>\u00a0: Introduction to embedded system design, system design methodologies, Introduction to System on Chip, \u00a0System on chip design flow, Embedded processor architecture, \u00a0Profiling approach, Hw-SW codesign.<\/p>\n

      Text books:<\/strong>\u00a0<\/strong><\/p>\n

        \n
      1. Verilog Digital System Design RT Level Synthesis, Testbench and Verification<\/b><\/strong>by Navabi, McGraw Hill (2005) ISBN-13:\u00a0978-0071445641<\/li>\n
      2. Fundamentals of Digital Logic with Verilog Design, By Stephen Brown, Zvonko Vranesic Tata McGraw-Hill edition.<\/li>\n
      3. Computer System Design System-on-Chip Michael J. Flynn Wayne Luk,published by Published by John Wiley & Sons (2011), ISBN 978-0-470-64336-5<\/li>\n<\/ol>\n

        Reference books:<\/strong><\/p>\n

        4. Embedded Core Design with FPGAs, Z. Navabi McGraw Hill (2007), ISBN 978-0-07-147481-8.<\/p>\n

        5. Synthesis and optimization of Digital Circuits by G.D.Michelli, Springer.<\/p>\n

        Name of the \u00a0Centre :CASEST<\/strong><\/p>\n

        Name of the Academic Program \u00a0M.Tech (Microelectronics and VLSI Design) <\/strong><\/p>\n

        Course Code: \u00a0MV404<\/strong>\u00a0Title of the Course: RF\/ Microwave ICs<\/strong><\/p>\n

        L-T-P: 3-1-0 \u00a0 Credits: 4<\/p>\n

        Prerequisite Course \/ Knowledge (If any): The following courses at the B.Tech or M.Sc level.<\/p>\n

          \n
        1. Electromagnetic Theory<\/b><\/strong><\/li>\n
        2. <\/b>Advanced Mathematical Methods<\/b><\/strong><\/li>\n<\/ol>\n

          Course Outcomes (COs) <\/strong><\/p>\n

          After completion of this course successfully, the students will be able to<\/p>\n

          CO-1: Analyze\u00a0the difference between high frequency ICs and conventional ICs and apply transmission line and distributed element based approaches to solve problems with high frequency circuits.<\/p>\n

          CO-2: Apply impedance matching \u00a0techniques for different circuit conditions and frequency ranges. Use of Smith charts.<\/p>\n

          CO-3 Evaluate\u00a0ways to miniaturize the high frequency passives, interconnects and active devices and also by multilayering.<\/p>\n

          CO-4 Analyze different types of planar transmission lines and their design considerations.<\/p>\n

          CO-5 Apply the design approach in planar circuits with filter as an example. (Lumped to distributed conversion).<\/p>\n

          CO-6 \u00a0Apply softwares to achieve high frequency circuit design goals along with IC 407 course.<\/p>\n

          CO-7 \u00a0Evaluate emerging high frequency miniaturization techniques through a Term Paper.<\/p>\n

          Mapping of Course Outcomes (COs) with Program Outcomes (POs)<\/strong><\/p>\n

          and Program Specific Outcomes (PSOs)<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n
          \u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\u00a0<\/strong>PSO5<\/strong><\/td>\n<\/tr>\n
          CO1<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
          CO2<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
          CO3<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
          CO4<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
          CO5<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
          CO6<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
          CO7<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

          \u00a0<\/strong>Detailed Syllabus: <\/strong><\/p>\n

          UNIT-1<\/b><\/strong>\u00a0High Frequency Electronics<\/p>\n

          Why RF communication?, Unique features of RF communication. Lumped vs. Distributed approach. Why RF circuits are to be treated differently in both active and passive devices? How Miniaturization leads to higher frequency operation? Introduction to high frequency ICs. Challenges and ways to miniaturize a high frequency circuit. Hybrid and integrated approach. High frequency ICs with lumped elements. MIC, MMIC and RFICs. Low frequency vs. High frequency models and parameters.<\/p>\n

          UNIT-II<\/b><\/strong>\u00a0Transmission Line Theory, Impedance Transformation and Matching<\/p>\n

          Review of EM Theory and Transmission lines. Impedance transformation and its effect on microwave circuits. Transmission line sections as circuit elements. Smith chart and admittance chart. Impedance matching techniques for narrow band and broadband operation. Impedance matching using T.line sections, quarter wave lines and lumped elements.<\/p>\n

          UNIT \u2013III<\/strong>\u00a0Planar Transmission Lines<\/p>\n

          Planar transmission lines that can be miniaturized: Striplines, Microstriplines, Coplanar waveguides. Design and analysis of microstrip and coplanar waveguide circuits. T.Line discontinuities as circuit elements.<\/p>\n

          UNIT \u2013IV<\/strong>\u00a0Materials, Fabrication and Miniaturization<\/p>\n

          Substrates for transmission lines \u2013 dielectrics vs semiconductors. Lumped L,C and R and their models. Parasitics in high frequency circuits and ways to model them.<\/p>\n

          Materials used for their realization and their properties: Substrates, conductors, semiconductors, dielectrics and magnetic materials. Micromachining for lumped elements and T.Lines, RF MEMS, Integrated inductors and surface integrated waveguides.<\/p>\n

          UNIT \u2013V<\/strong>\u00a0Microwave Filter Design, Realization and Testing.<\/p>\n

          Microwave filter design. Filters using transmission line sections. Kuroda\u2019s Identities. Richard\u2019s transformation. Microwave Resonators, Filters using resonators, Varactors and tuning techniques, On wafer probing and on wafer calibration techniques.<\/p>\n

          Text Books:<\/em><\/p>\n

          David M. Pozar, \u201cMicrowave Engineering,\u201d 2nd Edition, John Wiley 1998, ISBN 0-471-17096-8.<\/p>\n

          Peter A. Rizzi, \u201cMicrowave Engineering \u2013 Passive Circuits\u201d, PHI, ISBN \u00a081-203-1461-1<\/p>\n

          RFIC and MMIC design and technology, I.D. Robertson and S.Lucyszyn, IEE Circuits, Devices and Systems Series 13. ISBN-10 : 0852967861<\/p>\n

          Related IEEE Journal Papers<\/p>\n

          Reference Books:<\/i><\/em><\/p>\n

          K.<\/i><\/em>C. Gupta, Ramesh Garg, Inder Bahl, and Prakash Bhartia, \u201cMicrostrip Lines and Slotlines,\u201d Artech House, 2nd edition, 1996, ISBN: 089006766X.<\/p>\n

          T.C. Edwards and M. B. Steer, \u201cFoundations of Interconnect and Microstrip Design,\u201d John Wiley & Sons, 3rd edition, 2001, ISBN: 0471607010.<\/p>\n

          Mike Golio (Ed.), The RF and Microwave Handbook, CRC Press. ISBN: 9780849385926.<\/p>\n

          Novel technologies for microwave and millimeter-wave applications, Jean-Fu Kiang, Kluwer Academic Publishers. ISBN -10: 1441954015.<\/p>\n

           <\/p>\n

          Name of the \u00a0Centre : CASEST<\/strong><\/p>\n

          Name of the Academic Program \u00a0M.Tech (Microelectronics and VLSI Design) <\/strong><\/p>\n

          Course Code: \u00a0MV405: <\/strong><\/p>\n

          Title of the Course:\u00a0Numerical techniques for Microelectronics Simulation<\/strong><\/p>\n

          L-T-P: 2-0-0 \u00a0 Credits: 2<\/p>\n

          Prerequisite Course \/ Knowledge (If any): Nil<\/p>\n

          Course Outcomes (COs) <\/strong><\/p>\n

          After completion of this course successfully, the students will be able to<\/p>\n

          CO1: Recognize the procedure to solve non-linear algebraic problem which is employed for the interpretation of electrostatic potential of the device.<\/p>\n

          CO2: Describe the flow of carrier densities in semiconductor device and briefly review the non-linear iteration solution method used in numerical simulation.<\/p>\n

          CO3: Identify the carrier mobility along with scattering effect and growth of oxide layer on the material surface.<\/p>\n

          CO4: Examine the integrity of circuit design and predict the circuit behaviour.<\/p>\n

          CO5: Illustrate the circuits in terms of DC, AC, noise, distortion etc at simulation level.<\/p>\n\n\n\n\n\n\n\n\n
          \u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\u00a0<\/strong>PSO5<\/strong><\/td>\n<\/tr>\n
          CO1<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n\u00a0<\/td>\n1<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
          CO2<\/strong><\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n\u00a0<\/td>\n1<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
          CO3<\/strong><\/td>\n2<\/td>\n\u00a0<\/td>\n2<\/td>\n\u00a0<\/td>\n1<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
          CO4<\/strong><\/td>\n2<\/td>\n\u00a0<\/td>\n3<\/td>\n\u00a0<\/td>\n1<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
          CO5<\/strong><\/td>\n2<\/td>\n\u00a0<\/td>\n3<\/td>\n\u00a0<\/td>\n1<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n\u00a0<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

          Note: \u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n

          \u00a0<\/strong>Detailed Syllabus:<\/strong><\/p>\n

          \u00a0<\/strong>Module-I: <\/b><\/strong>Numerical Analysis Review: Direct solution methods of partial differential equations, Iterative solution methods of partial differential equations.<\/p>\n

          Module \u2013II:<\/strong>\u00a0Drift-Diffusion Model: Physical limitations, Modeling of Continuity equation, Bipolar semiconductor equations, Normalization and scaling, Gummel\u2019s iteration method, Newton\u2019s method, Time-dependent simulations, \u00a0Examples of Application of DD model.<\/p>\n

          Module \u2013 III:<\/strong>\u00a0Mobility models used in commercial simulators. Models for thermal oxidation (dry and wet).<\/p>\n

          Module IV:<\/strong>\u00a0Introduction to SPICE modeling, modeling of elements (like resistor, capacitor, inductor, diode, BJT, JFET, MOS capacitor and MOSFET). Introduction to setting model parameters, parameter extraction and model validation. Overview of BSIM and EKV model for MOSFETs.<\/p>\n

          Module V:<\/strong>\u00a0Circuit simulation techniques, DC analysis, AC analysis, transient analysis, SPICE Modeling of Process Variation, Process corners, Monte Carlo simulation, and sensitivity\/worst case analysis, Simulation of digital and analog circuits, transfer function, frequency response, Noise analysis, distortion and spectral analysis, Basics of Finite element Analysis(FEA) and FDTD methods.<\/p>\n

          Reference books<\/strong><\/p>\n

            \n
          1. Y. Tsividis, \u201cOperation and modeling of MOS transistors\u201d,2 nd Edition, McGraw-Hill, 1999.<\/li>\n
          2. Paul W. Tuinenga, \u201cSPICE: A Guide to Circuit Simulation and Analysis Using PSpice\u201d, 3 rd Edition, Pearson, 2006.<\/li>\n
          3. Paolo Antognetti and Giuseppe Massobrio, \u201cSemiconductor Device Modeling with SPICE\u201d, 2nd Edition, Tata McGraw-Hill, 2010.<\/li>\n
          4. BSIM Model (http:\/\/www-device.eecs.berkeley.edu\/bsim\/)<\/li>\n
          5. EKV Model (http:\/\/ekv.epfl.ch\/)<\/li>\n<\/ol>\n

            \u00a0<\/strong>\u00a0<\/strong><\/p>\n

            Name of the Centre: CASEST<\/strong><\/p>\n

            Name of the Academic Program \u00a0M.Tech (IC Technology)<\/strong><\/p>\n

            Course Code: \u00a0MV406 , <\/strong>Title of the Course : Microelectronics Simulation Laboratory<\/strong><\/p>\n

            L-T-P: \u00a01-0-3 \u00a0 Credits: 2<\/p>\n

            Prerequisite Course \/ Knowledge (If any): Basics of semiconductor devices and methods of fabrication, at BTech level.<\/p>\n

            Course Outcomes (COs) <\/strong><\/p>\n

            \u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n

            CO-1: Test discrete semiconductor devices using an industry standard method,\u00a0analyse and interpret results.<\/p>\n

            CO-2: Explain the concepts of various device simulation program.<\/p>\n

            CO-3: Simulate device and circuit performance:Application, validation and\u00a0interpretation of results.<\/p>\n

            CO-4: Evaluate the performance of various semiconductor devices and\u00a0Circuits.<\/p>\n

            CO-5: Communicate the results of all experiments in the form of a written technical report.<\/p>\n

            \u00a0<\/strong>Mapping of Course Outcomes (COs) with Program Outcomes (POs)<\/strong><\/p>\n

            and Program Specific Outcomes (PSOs)<\/strong><\/p>\n\n\n\n\n\n\n\n\n
            \n

            \u00a0<\/strong><\/p>\n<\/td>\n

            		PO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\nPSO5<\/strong><\/td>\n<\/tr>\n
            CO1<\/strong><\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n2<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\n3<\/td>\n1<\/td>\n<\/tr>\n
            CO2<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n0<\/td>\n2<\/td>\n0<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
            CO3<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n0<\/td>\n2<\/td>\n0<\/td>\n3<\/td>\n3<\/td>\n<\/tr>\n
            CO4<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
            CO5<\/strong><\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n3<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n2<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

            Note: \u20183\u2019 in the box for \u2018High-level\u2019mapping, 2 for \u2018Medium-level\u2019mapping, 1 for \u2018Low\u2019-level\u2019mapping<\/p>\n

            Detailed Syllabus:<\/strong><\/p>\n

              \n
            1. Device characterization using Device Analyser.<\/li>\n
            2. Process Simulation-(ion implantation, diffusion, oxidation).<\/li>\n
            3. Device Simulation- (p-n Diode, Schottky diode, MOSFET).<\/li>\n
            4. Circuit Simulation- \u00a0(MOSFET based circuits).<\/li>\n<\/ol>\n

              Text books: <\/strong><\/p>\n

                \n
              1. “Semiconductor Material and Device Characterization” by Dieter K. Schroder(Wiley-IEEE Press; 3 edition (2015))<\/li>\n
              2. Science and engineering of microelectronic Fabrication by Stephen CampbellOxford (University Press; Second edition (2012))<\/li>\n
              3. VLSI Technology M.Sze(McGraw Hill Education; 2 edition (2017))<\/li>\n<\/ol>\n

                \u00a0<\/strong><\/p>\n

                \u00a0<\/strong>Name of the Centre: CASEST<\/strong><\/p>\n

                \u00a0<\/strong>Name of the Academic Program \u00a0M.Tech (Microelectronics and VLSI Design) \u00a0<\/strong><\/p>\n

                Course Code: \u00a0MV407<\/strong>\u00a0<\/strong>Title of the Course:\u00a0\u00a0IC Design Laboratory<\/strong><\/p>\n

                L-T-P: \u00a00+0-6 \u00a0\u00a0 Credits: 3<\/p>\n

                Prerequisite Course \/ Knowledge (If any): MV402 and MV451 courses<\/p>\n

                Course Outcomes (COs) <\/strong><\/p>\n

                \u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n

                CO-1: Design and verify the functionality of \u00a0\u00a0combinational and sequential circuits using Verilog HDL.<\/p>\n

                CO2: Implement and carry-out on chip debugging of the digital design on FPGA.<\/p>\n

                CO3: Design and simulate the basic analog integrated circuits like CMOS amplifiers and biasing circuits.<\/p>\n

                CO4: Design of integrated circuits for target specifications and checking the robustness of the design at different process corners<\/p>\n

                CO5: Implement physical design of integrated circuits, DRC and LVS check, post-layout extracted simulation.<\/p>\n

                CO6: Communicate the results of the experiment in the form of written technical report.<\/p>\n

                Mapping of Course Outcomes (Cos) with Program Outcomes (Pos)<\/strong><\/p>\n

                and Program Specific Outcomes (PSOs)<\/strong>\u00a0<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n
                \u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\n

                \u00a0<\/strong>PSO5<\/strong><\/p>\n<\/td>\n<\/tr>\n

                CO1<\/strong><\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n–<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n<\/tr>\n
                CO2<\/strong><\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n–<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
                CO3<\/strong><\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n
                CO4<\/strong><\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
                CO5<\/strong><\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n<\/tr>\n
                CO6<\/strong><\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n2<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

                \u00a0<\/strong>Note: \u20183\u2019 in the box for \u2018High-level\u2019 mapping, 2 for \u2018Medium-level\u2019 mapping, 1 for \u2018Low\u2019-level\u2019 mapping<\/p>\n

                Detailed syllabus: <\/strong><\/p>\n

                List of experiments and mini-projects<\/p>\n

                1: Vivado Design Flow<\/p>\n

                2: Synthesizing a RTL Design<\/p>\n

                3: Implementing the Design<\/p>\n

                4: Using the IP Catalog and IP Integrator<\/p>\n

                5: Hardware Debugging<\/p>\n

                6: Analog and Mixed Signal IC Design Lab Projects<\/p>\n

                a. CS and CG amplifiers with different loads, e.g., resistive, diode connected, current source<\/p>\n

                b. Current mirrors, e.g., basic current mirror, cascode current mirror<\/p>\n

                c. Differential amplifier<\/p>\n

                d. Operational Transconductance amplifiers<\/p>\n

                 <\/p>\n

                Name of the \u00a0Centre :CASEST<\/strong><\/p>\n

                Name of the Academic Program \u00a0M.Tech (Microelectronics and VLSI Design) \u00a0<\/strong><\/p>\n

                \u00a0<\/strong>Course Code: \u00a0MV 408<\/strong>\u00a0\u00a0Title of the Course:\u00a0RF IC Laboratory<\/strong><\/p>\n

                L-T-P: \u00a00-0-4 \u00a0\u00a0 Credits: 2<\/p>\n

                Prerequisite Course \/ Knowledge (If any): It is the Lab component of the IC403 RF\/Microwave ICs Course.<\/p>\n

                Course Outcomes (COs) <\/strong><\/p>\n

                \u00a0<\/strong>After completion of this course successfully, the students will be able to<\/p>\n

                CO-1: Apply microwave measurement techniques using advanced measurement facilities like VNA.<\/p>\n

                CO-2: Apply the usage of EDA tools in doing high frequency circuit Design and Simulation.<\/p>\n

                CO-3 Apply EDA tools to Design and Simulate passive MIC circuits and active microwave circuits.<\/p>\n

                CO-4 Apply EDA tools for doing Full wave simulations by Method of Moments, FEM and FDTD.<\/p>\n

                CO-5 Analyze EDA tools to do Fullwave simulation and analysis of layout of high frequency circuits.<\/p>\n

                CO-6 Create high frequency circuits using EDA tools and simulate them.<\/p>\n

                CO-7 Fabricate the high frequency circuits.<\/p>\n

                CO-8 Communicate the results of these experiments in the form of a written technical report.<\/p>\n

                Mapping of Course Outcomes (COs) with Program Outcomes (POs)<\/strong><\/p>\n

                and Program Specific Outcomes (PSOs)<\/strong><\/p>\n\n\n\n\n\n\n\n\n\n\n\n
                \u00a0<\/strong><\/td>\nPO1<\/strong><\/td>\nPO2<\/strong><\/td>\nPO3<\/strong><\/td>\nPO4<\/strong><\/td>\nPO5<\/strong><\/td>\nPO6<\/strong><\/td>\nPSO1<\/strong><\/td>\nPSO2<\/strong><\/td>\nPSO3<\/strong><\/td>\nPSO4<\/strong><\/td>\n\n

                \u00a0<\/strong>PSO5<\/strong><\/p>\n<\/td>\n<\/tr>\n

                CO1<\/strong><\/td>\n3<\/td>\n2<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
                CO2<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
                CO3<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
                CO4<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
                CO5<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n2<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
                CO6<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
                CO7<\/strong><\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n
                CO8<\/strong><\/td>\n3<\/td>\n1<\/td>\n1<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n1<\/td>\n2<\/td>\n3<\/td>\n1<\/td>\n3<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

                List of experiments<\/strong>\/ Mini -projects<\/strong><\/p>\n

                  \n
                1. Microwave measurement techniques for devices and circuits with Vector Network Analyzer, Power Meter and On Wafer Probing System.<\/li>\n
                2. Tools for high frequency design, Familiarization of EDA tools for RF\/ Microwave IC design and simulation, Usage of Models and Libraries for EDA tools, Design Examples (using both active and passive devices).<\/li>\n
                3. Fullwave analysis in simulation and analysis of circuit layouts and housings using Method of Moments, FEM and FDTD.<\/li>\n
                4. Design and simulation of active and passive microwave integrated circuits using EDA tools.\n